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US4939392A Output circuit for driving a memory device output lead including a three-state inverting buffer and a transfer gate coupled between the buffer input lead and the buffer output lead 失效
标题翻译：用于驱动存储器件输出引线的输出电路，其包括耦合在缓冲器输入引线和缓冲器输出引线之间的三态反相缓冲器和传输栅极
公开(公告)号：US4939392A
公开(公告)日：1990-07-03
申请号：US231123
申请日：1988-08-11
申请人： Alexander Shubat , Barmak Sani
发明人： Alexander Shubat , Barmak Sani
IPC分类号： H03K19/0185 , H03K19/094
CPC分类号： H03K19/018557 , H03K19/09429
摘要： A novel circuit is coupled to a memory device sense amplifier and a memory device output pin for driving the output pin with data. The circuit includes a first inverter (18) and a second inverter (100) coupled to the first inverter. Transfer gates (30, 104) are coupled across the input and output leads of the first and second inverters, respectively. During a first mode of operation, the first and second transfer gates are closed and the second inverter is three-stated so that the input and output leads of the first and second inverters are held at a voltage between VCC and ground. When it is desired to drive the memory device output pin with data, the first and second transfer gates open, and the second inverter leaves the three-state mode and goes into a low output impedance mode. Because the input and output leads of the first and second inverters are held at a voltage between VCC and ground when the transfer gates are closed, when the transfer gates open, the delay between the time the transfer gates open and the time valid output data appears on the output lead of the second inverter is minimized. The second inverter comprises large transistors and can therefore provide a large output current. However, because the second inverter is three-stated when the second transfer gate is closed, the circuit draws minimal power when the first and second transfer gates are closed.
摘要翻译：一个新颖的电路耦合到存储器件读出放大器和存储器件输出引脚，用于用数据驱动输出引脚。电路包括耦合到第一反相器的第一反相器（18）和第二反相器（100）。转移门（30,104）分别耦合在第一和第二逆变器的输入和输出引线上。在第一操作模式下，第一和第二传输门关闭，第二反相器是三态的，使得第一和第二反相器的输入和输出引线保持在VCC和地之间的电压。当需要用数据驱动存储器件输出引脚时，第一和第二传输门打开，第二个反相器退出三态模式并进入低输出阻抗模式。由于当传输门关闭时，第一和第二反相器的输入和输出引线保持在VCC和地之间的电压，当传输门打开时，传输门打开时间和时间有效输出数据之间的延迟出现在第二反相器的输出引线上最小化。第二反相器包括大晶体管，因此可以提供大的输出电流。然而，由于当第二传输门关闭时第二反相器是三态的，所以当第一和第二传输门关闭时，电路消耗最小的功率。

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