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1. 发明申请

US20130094580A1 DETECTING AVAILABILITIES OF NEIGHBORING VIDEO UNITS FOR VIDEO CODING 有权
标题翻译：检测视频编码视频单元的可行性
公开(公告)号：US20130094580A1
公开(公告)日：2013-04-18
申请号：US13418107
申请日：2012-03-12
申请人： Bo Zhou , Gurunath Ramaswamy , Karthic Veera , Peisong Chen , Muhammed Zeyd Coban , Junchen Du , Suhail Jalil
发明人： Bo Zhou , Gurunath Ramaswamy , Karthic Veera , Peisong Chen , Muhammed Zeyd Coban , Junchen Du , Suhail Jalil
IPC分类号： H04N7/32
CPC分类号： H04N19/13 , H04N19/192 , H04N19/423 , H04N19/91 , H04N19/96
摘要： As part of a video encoding or decoding operation on video data, a video coder performs a coding operation for a current video unit of the video data. As part of performing the coding operation for the current video unit, the video coder determines the availabilities of one or more video units that neighbor the current video unit. In order to determine the availability of a video unit that neighbors the current video unit, the video coder identifies, based on availabilities of video units that neighbor a parent video unit of the current video unit, an entry in a lookup table. The identified entry indicates the availability of the video unit that neighbors the current video unit. The video coder then performs a coding operation on the current video unit based on whether the video unit that neighbors the current video unit is available.
摘要翻译：作为对视频数据的视频编码或解码操作的一部分，视频编码器对视频数据的当前视频单元执行编码操作。作为执行当前视频单元的编码操作的一部分，视频编码器确定与当前视频单元相邻的一个或多个视频单元的可用性。为了确定与当前视频单元相邻的视频单元的可用性，视频编码器基于与当前视频单元的父视频单元相邻的视频单元的可用性来识别查找表中的条目。所标识的条目指示与当前视频单元相邻的视频单元的可用性。然后，视频编码器基于与当前视频单元相邻的视频单元是否可用，对当前视频单元执行编码操作。

2. 发明授权

US09838692B2 Detecting availabilities of neighboring video units for video coding 有权
公开(公告)号：US09838692B2
公开(公告)日：2017-12-05
申请号：US13418107
申请日：2012-03-12
申请人： Bo Zhou , Gurunath Ramaswamy , Karthic Veera , Peisong Chen , Muhammed Zeyd Coban , Junchen Du , Suhail Jalil
发明人： Bo Zhou , Gurunath Ramaswamy , Karthic Veera , Peisong Chen , Muhammed Zeyd Coban , Junchen Du , Suhail Jalil
IPC分类号： H04N19/13 , H04N19/96 , H04N19/91 , H04N19/192 , H04N19/423
CPC分类号： H04N19/13 , H04N19/192 , H04N19/423 , H04N19/91 , H04N19/96
摘要： As part of a video encoding or decoding operation on video data, a video coder performs a coding operation for a current video unit of the video data. As part of performing the coding operation for the current video unit, the video coder determines the availabilities of one or more video units that neighbor the current video unit. In order to determine the availability of a video unit that neighbors the current video unit, the video coder identifies, based on availabilities of video units that neighbor a parent video unit of the current video unit, an entry in a lookup table. The identified entry indicates the availability of the video unit that neighbors the current video unit. The video coder then performs a coding operation on the current video unit based on whether the video unit that neighbors the current video unit is available.

3. 发明授权

US08855446B2 Accelerated video compression multi-tap filter and bilinear interpolator 有权
标题翻译：加速视频压缩多抽头滤波器和双线性内插器
公开(公告)号：US08855446B2
公开(公告)日：2014-10-07
申请号：US13450734
申请日：2012-04-19
申请人： Bo Zhou , Mao Zeng , Junchen Du , Lucian Codrescu , Suhail Jalil
发明人： Bo Zhou , Mao Zeng , Junchen Du , Lucian Codrescu , Suhail Jalil
IPC分类号： G06K9/32
CPC分类号： H04N19/523 , H04N19/43 , H04N19/80
摘要： A set of even interpolated sub-pixels is formed based on a pixel window and a tap coefficient register having a tap coefficient set, the pixel window is shifted and, applying the tap coefficient register a set of odd interpolated pixels is formed. The set of even interpolated sub-pixels and the set of odd interpolated sub-pixels are accumulated, repeatedly, until a termination condition is let. In the accumulating, the tap coefficient register is updated with another tap coefficient set, the pixel window is shifted, and the even interpolated pixels are incremented, the pixel window is then shifted again and the odd interpolated pixels are incremented.
摘要翻译：基于像素窗口和具有抽头系数集的抽头系数寄存器形成一组偶数内插子像素，像素窗口被移位，并且形成一组奇插值像素。偶数内插子像素组和奇数内插子像素组被重复累积，直到终止条件为let。在累积中，抽头系数寄存器用另一个抽头系数组更新，像素窗口被移位，并且偶数内插像素递增，然后像素窗口再次移位，并且奇数内插像素增加。

4. 发明申请

US20130279827A1 Accelerated Video Compression Multi-Tap Filter and Bilinear Interpolator 有权
标题翻译：加速视频压缩多点滤波器和双线性插值器
公开(公告)号：US20130279827A1
公开(公告)日：2013-10-24
申请号：US13450734
申请日：2012-04-19
申请人： Bo Zhou , Mao Zeng , Junchen Du , Lucian Codrescu , Suhail Jalil
发明人： Bo Zhou , Mao Zeng , Junchen Du , Lucian Codrescu , Suhail Jalil
IPC分类号： G06K9/32
CPC分类号： H04N19/523 , H04N19/43 , H04N19/80
摘要： A set of even interpolated sub-pixels is formed based on a pixel window and a tap coefficient register having a tap coefficient set, the pixel window is shifted and, applying the tap coefficient register a set of odd interpolated pixels is formed. The set of even interpolated sub-pixels and the set of odd interpolated sub-pixels are accumulated, repeatedly, until a termination condition is let. In the accumulating, the tap coefficient register is updated with another tap coefficient set, the pixel window is shifted, and the even interpolated pixels are incremented, the pixel window is then shifted again and the odd interpolated pixels are incremented.
摘要翻译：基于像素窗口和具有抽头系数集的抽头系数寄存器形成一组偶数内插子像素，像素窗口被移位，并且形成一组奇插值像素。偶数内插子像素组和奇数内插子像素组被重复累积，直到终止条件为let。在累积中，抽头系数寄存器用另一个抽头系数组更新，像素窗口被移位，并且偶数内插像素递增，然后像素窗口再次移位，并且奇数内插像素增加。

5. 发明申请

US20130188732A1 Multi-Threaded Texture Decoding 审中-公开
标题翻译：多线程纹理解码
公开(公告)号：US20130188732A1
公开(公告)日：2013-07-25
申请号：US13354364
申请日：2012-01-20
申请人： Bo Zhou , Shu Xiao , Junchen Du , Suhail Jalil
发明人： Bo Zhou , Shu Xiao , Junchen Du , Suhail Jalil
IPC分类号： H04N7/26
CPC分类号： H04N19/436 , H04N19/423 , H04N19/44 , H04N19/82
摘要： A method for performing texture decoding in a multi-threaded processor includes substantially simultaneously decoding, in multiple hardware threads, at least two macro-blocks of a VP8 frame. Each hardware thread decodes one macro-block at a time. The method may also include assigning a macro-block from the at least two macro-blocks of the VP8 frame to a hardware thread of the multi-threaded processor.
摘要翻译：用于在多线程处理器中执行纹理解码的方法包括在多个硬件线程中基本上同时解码VP8帧的至少两个宏块。每个硬件线程一次解码一个宏块。该方法还可以包括从VP8帧的至少两个宏块分配到多线程处理器的硬件线程的宏块。

6. 发明申请

US20120262542A1 DEVICES AND METHODS FOR WARPING AND HOLE FILLING DURING VIEW SYNTHESIS 审中-公开
标题翻译：在视图合成期间的加热和孔填充的装置和方法
公开(公告)号：US20120262542A1
公开(公告)日：2012-10-18
申请号：US13301319
申请日：2011-11-21
申请人： Karthic Veera , Ying Chen , Junchen Du , Marta Karczewicz
发明人： Karthic Veera , Ying Chen , Junchen Du , Marta Karczewicz
IPC分类号： H04N9/74 , H04N13/00 , H04N5/14
CPC分类号： G06T5/005 , G06T2207/10021
摘要： Implementations include methods and systems for a converting reference images or video to 3D images or video. A two-step conversion is described which accomplishes warping and hole filling on a pixel-by-pixel basis. In one implementation, of a plurality of pixel values of a reference image at a plurality of first collinear pixels locations are successively mapped to a respective plurality of second pixel locations of a destination image. Between two of the mappings, a location of a hole between two of the second pixel locations may be identified and filled.
摘要翻译：实现包括将参考图像或视频转换为3D图像或视频的方法和系统。描述了在逐个像素的基础上实现翘曲和孔填充的两步转换。在一个实现中，在多个第一共线像素位置处的参考图像的多个像素值中的像素值被连续映射到目的地图像的相应多个第二像素位置。在两个映射之间，可以识别并填充两个第二像素位置之间的孔的位置。

7. 发明申请

US20130077690A1 Firmware-Based Multi-Threaded Video Decoding 审中-公开
标题翻译：基于固件的多线程视频解码
公开(公告)号：US20130077690A1
公开(公告)日：2013-03-28
申请号：US13241322
申请日：2011-09-23
申请人： Jian Wei , Girish Jian , Junchen Du
发明人： Jian Wei , Girish Jian , Junchen Du
IPC分类号： H04N7/26 , H04N7/32
CPC分类号： H04N19/436 , H04N19/176 , H04N19/42 , H04N19/423 , H04N19/44
摘要： Embodiments of the present disclosure provide electronic devices and methods for equipping a multi-threaded processor with firmware instructions to configure threads to perform dedicated functions to expedite decoding of video data. In a particular embodiment, an electronic device includes a multi-threaded processor and a memory. The memory includes firmware including instructions executable by the multi-threaded processor, without use of a dedicated hardware macroblock decoding module, to decode video data compliant with a VP6 format.
摘要翻译：本公开的实施例提供了用于为多线程处理器配备固件指令以配置线程以执行专用功能以加速视频数据的解码的电子设备和方法。在特定实施例中，电子设备包括多线程处理器和存储器。存储器包括固件，包括可由多线程处理器执行的指令，而不使用专用硬件宏块解码模块来解码符合VP6格式的视频数据。

8. 发明申请

US20100086057A1 METHOD AND APPARATUS FOR REDUCING BUS TRAFFIC OF A TEXTURE DECODING MODULE IN A VIDEO DECODER 有权
标题翻译：用于减少视频解码器中纹理解码模块的总线交通的方法和装置
公开(公告)号：US20100086057A1
公开(公告)日：2010-04-08
申请号：US12247720
申请日：2008-10-08
申请人： Shu Xiao , Junchen Du
发明人： Shu Xiao , Junchen Du
IPC分类号： H04N7/26
CPC分类号： H04N19/93 , H04N19/132 , H04N19/18 , H04N19/428 , H04N19/44 , H04N19/46 , H04N19/61 , H04N19/70
摘要： Techniques for reducing bus traffic during texture decoding of a video bitstream are provided. In one configuration, a wireless communication device (e.g., cellular phone, etc.) comprises a processor configured to execute instructions operative to decode and separate in a bitstream macroblock (MB) information and residual packet data. The residual packet data is used to generate codec-independent non-zero MB-packets having a universal order that is codec independent. The codec-independent non-zero MB-packets and MB information are then used for reconstructing pixels of a respective frame of the video bitstream.
摘要翻译：提供了在视频比特流的纹理解码期间减少总线流量的技术。在一种配置中，无线通信设备（例如，蜂窝电话等）包括被配置为执行操作以在比特流宏块（MB）信息和残余分组数据中解码和分离的指令的处理器。残留分组数据用于生成具有独立于编解码器的通用顺序的与编解码器无关的非零MB分组。然后将与编解码器无关的非零MB分组和MB信息用于重构视频比特流的相应帧的像素。

9. 发明授权

US08576916B2 Method and apparatus for reducing bus traffic of a texture decoding module in a video decoder 有权
标题翻译：用于减少视频解码器中的纹理解码模块的总线流量的方法和装置
公开(公告)号：US08576916B2
公开(公告)日：2013-11-05
申请号：US12247720
申请日：2008-10-08
申请人： Shu Xiao , Junchen Du
发明人： Shu Xiao , Junchen Du
IPC分类号： H04N7/12 , H04N11/04
CPC分类号： H04N19/93 , H04N19/132 , H04N19/18 , H04N19/428 , H04N19/44 , H04N19/46 , H04N19/61 , H04N19/70
摘要： Techniques for reducing bus traffic during texture decoding of a video bitstream are provided. In one configuration, a wireless communication device (e.g., cellular phone, etc.) comprises a processor configured to execute instructions operative to decode and separate in a bitstream macroblock (MB) information and residual packet data. The residual packet data is used to generate codec-independent non-zero MB-packets having a universal order that is codec independent. The codec-independent non-zero MB-packets and MB information are then used for reconstructing pixels of a respective frame of the video bitstream.
摘要翻译：提供了在视频比特流的纹理解码期间减少总线流量的技术。在一种配置中，无线通信设备（例如，蜂窝电话等）包括被配置为执行操作以在比特流宏块（MB）信息和残余分组数据中解码和分离的指令的处理器。残留分组数据用于生成具有独立于编解码器的通用顺序的与编解码器无关的非零MB分组。然后将与编解码器无关的非零MB分组和MB信息用于重构视频比特流的相应帧的像素。

10. 发明授权

US07895250B2 Fixed point integer division techniques for AC/DC prediction in video coding devices 有权
标题翻译：用于视频编码设备中AC / DC预测的定点整数除法技术
公开(公告)号：US07895250B2
公开(公告)日：2011-02-22
申请号：US11137069
申请日：2005-05-25
申请人： Shu Xiao , Junchen Du , Tao Shen
发明人： Shu Xiao , Junchen Du , Tao Shen
IPC分类号： G06F7/38
CPC分类号： H04N19/18 , G06F7/4873 , G06F7/49963 , G06F7/535 , G06F2101/12 , G06F2207/5356 , H04N19/42 , H04N19/593 , H04N19/61
摘要： The disclosure describes a method for performing a fixed point calculation of a floating point operation (A // B) in a coding device, wherein A // B represents integer division of A divided by B rounded to a nearest integer. The method may comprise selecting an entry from a lookup table (LUT) having entries generated as an inverse function of an index B, wherein B defines a range of values that includes every DC scalar value and every quantization parameter associated with a coding standard, and calculating A // B for coding according to the coding standard based on values A, B1 and B2, wherein B1 and B2 comprise high and low portions of the selected entry of the LUT. The techniques may simplify digital signal processor (DSP) implementations of video coders, and are specifically useful for MPEG-4 coders and possibly others.
摘要翻译：本公开描述了一种用于在编码装置中执行浮点运算（A // B）的固定点计算的方法，其中A // B表示A除以被舍入为最接近整数的B的整数除法。该方法可以包括从具有作为索引B的反函数生成的条目的查找表（LUT）中选择条目，其中B定义包括每个DC标量值和与编码标准相关联的每个量化参数的值的范围，以及基于值A，B1和B2，根据编码标准计算A // B进行编码，其中B1和B2包括LUT的所选条目的高和低部分。这些技术可以简化视频编码器的数字信号处理器（DSP）实现，并且对MPEG-4编码器和可能的其它编码器特别有用。

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