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1. 发明授权

US07804317B1 Test device for determining charge damage to a transistor 有权
标题翻译：用于确定对晶体管的电荷损坏的测试装置
公开(公告)号：US07804317B1
公开(公告)日：2010-09-28
申请号：US11583758
申请日：2006-10-19
申请人： Biju Parameshwaran , Sriram Madhavan , Andrew E. Carlson
发明人： Biju Parameshwaran , Sriram Madhavan , Andrew E. Carlson
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , H01L22/34
摘要： According to one exemplary embodiment, a test device includes a transistor situated on a substrate. The test device further includes a protection device coupled by a fuse to a gate of the transistor in an interconnect metal layer, where the interconnect metal layer is formed over the substrate. The fuse allows the protection device to be decoupled from the gate of the transistor prior to testing the transistor. The test device further includes first and second contact pads formed over the substrate and coupled to respective terminals of the fuse to provide access to the fuse. A current can be applied between the first and second contacts pads to cause the fuse to open to decouple the protection device from the gate of the transistor. The test device further includes an antenna coupled to the gate of the transistor with interconnect metal segments for accumulating electrical charge during wafer processing.
摘要翻译：根据一个示例性实施例，测试装置包括位于基板上的晶体管。测试装置还包括保护装置，其通过熔丝耦合到互连金属层中的晶体管的栅极，其中互连金属层形成在衬底上。熔丝允许保护器件在测试晶体管之前与晶体管的栅极分离。测试装置还包括形成在衬底上的第一和第二接触焊盘，并且耦合到熔丝的相应端子以提供对熔丝的接触。可以在第一和第二接触焊盘之间施加电流以使保险丝断开以将保护装置与晶体管的栅极分离。测试装置还包括天线，其耦合到具有用于在晶片处理期间累积电荷的互连金属段的晶体管的栅极。

2. 发明授权

US07205164B1 Methods for fabricating magnetic cell junctions and a structure resulting and/or used for such methods 有权
标题翻译：用于制造磁性细胞结的方法和产生和/或用于这种方法的结构
公开(公告)号：US07205164B1
公开(公告)日：2007-04-17
申请号：US11039301
申请日：2005-01-19
申请人： Sam Geha , Benjamin C. E. Schwarz , Chang Ju Choi , Biju Parameshwaran , Eugene Y. Chen , Helen L. Chung , Kamel Ounadjela , Witold Kula
发明人： Sam Geha , Benjamin C. E. Schwarz , Chang Ju Choi , Biju Parameshwaran , Eugene Y. Chen , Helen L. Chung , Kamel Ounadjela , Witold Kula
IPC分类号： H01L21/00
CPC分类号： H01L21/02071 , B82Y10/00 , H01L21/02063 , H01L43/12
摘要： Methods for patterning a magnetic cell junction and a topography used for and/or resulting from such methods are provided. In particular, a method is provided which includes etching portions of a topography adjacent to a patterned photoresist layer to a level within a cap film of the topography, removing etch residues from the topography and subsequently etching the remaining portions of the cap film to expose an uppermost magnetic layer. Another method is provided which includes patterning a dielectric mask layer above a patterned upper portion of a magnetic cell junction and ion milling a lower portion of the magnetic cell junction in alignment with the mask layer. An exemplary topography which may result and/or may be used for such methods includes a stack of layers having a dual layer cap film arranged above at least two magnetic layers spaced apart by a tunneling layer.
摘要翻译：提供了用于图案化磁性细胞结的方法和用于和/或由这些方法产生的形貌。特别地，提供了一种方法，其包括将与图案化的光致抗蚀剂层相邻的形貌的部分蚀刻到地形的盖膜内的水平，从形貌去除蚀刻残留物，随后蚀刻盖膜的剩余部分以暴露最上层的磁性层。提供了另一种方法，其包括将介电掩模层图案化在磁性细胞结的图案化的上部上方，并离子铣削与掩模层对准的磁性细胞结的下部。可能导致和/或可用于这种方法的示例性形貌包括具有布置在至少两个由隧道层间隔开的磁性层之上的双层帽膜的层叠。

3. 发明授权

US06794269B1 Method for and structure formed from fabricating a relatively deep isolation structure 有权
标题翻译：通过制造相对较深的隔离结构形成的方法和结构
公开(公告)号：US06794269B1
公开(公告)日：2004-09-21
申请号：US10324989
申请日：2002-12-20
申请人： Prabhuram Gopalan , Biju Parameshwaran , Krishnaswamy Ramkumar , Hanna Bamnolker , Sundar Narayanan
发明人： Prabhuram Gopalan , Biju Parameshwaran , Krishnaswamy Ramkumar , Hanna Bamnolker , Sundar Narayanan
IPC分类号： H01L2176
CPC分类号： H01L21/763 , H01L21/76202
摘要： A method is provided which includes forming a deep isolation structure within a semiconductor topography. In some cases, the method may include forming a first isolation structure within a semiconductor layer and etching an opening within the isolation structure to expose the semiconductor layer. In addition, the method may include etching the semiconductor layer to form a trench extending through the isolation structure and at least part of the semiconductor layer. In some cases, the method may include removing part of a first fill layer deposited within the trench such that an upper surface of the fill layer is below an upper portion of the trench. In such an embodiment, the vacant portion of the trench may be filled with a second fill layer. In yet other embodiments, the method may include planarizing the first fill layer within the trench and subsequently oxidizing an upper portion of the fill layer.
摘要翻译：提供了一种方法，其包括在半导体形貌内形成深度隔离结构。在一些情况下，该方法可以包括在半导体层内形成第一隔离结构并蚀刻隔离结构内的开口以暴露半导体层。此外，该方法可以包括蚀刻半导体层以形成延伸穿过隔离结构和半导体层的至少一部分的沟槽。在一些情况下，该方法可以包括去除沉积在沟槽内的第一填充层的部分，使得填充层的上表面在沟槽的上部下方。在这样的实施例中，沟槽的空缺部分可以填充第二填充层。在其他实施例中，该方法可以包括平坦化沟槽内的第一填充层，随后氧化填充层的上部。

4. 发明授权

US06969689B1 Method of manufacturing an oxide-nitride-oxide (ONO) dielectric for SONOS-type devices 有权
标题翻译：用于SONOS型器件的氧化物 - 氮化物（ONO）电介质的制造方法
公开(公告)号：US06969689B1
公开(公告)日：2005-11-29
申请号：US10184715
申请日：2002-06-28
申请人： Krishnaswamy Ramkumar , Manuj Rathor , Biju Parameshwaran , Loren Lancaster
发明人： Krishnaswamy Ramkumar , Manuj Rathor , Biju Parameshwaran , Loren Lancaster
IPC分类号： H01L21/28 , H01L21/31 , H01L21/314 , H01L21/469 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11568 , H01L21/28282 , H01L21/3144 , H01L27/115
摘要： A method of forming oxide-nitride-oxide (ONO) dielectric of a SONOS-type nonvolatile storage device is disclosed. According to a first embodiment, a method may include the steps of forming a tunneling dielectric (step 102), forming a charge storing dielectric (step 104), and forming a top insulating layer (step 106) all in the same wafer processing tool. According to various aspects of the embodiments, all layers of an ONO dielectric of a SONOS-type device may be formed in the same general temperature range. Further, a tunneling dielectric may include a tunnel oxide formed with a long, low pressure oxidation, and a top insulating layer may include silicon dioxide formed with a preheated source gas.
摘要翻译：公开了一种形成SONOS型非易失性存储装置的氧化物 - 氧化物 - 氧化物（ONO）电介质的方法。根据第一实施例，一种方法可以包括以下步骤：形成隧道电介质（步骤102），形成电荷存储电介质（步骤104），以及在相同的晶片处理工具中形成顶部绝缘层（步骤106）。根据实施例的各个方面，SONOS型器件的ONO电介质的所有层可以形成在相同的一般温度范围内。此外，隧道电介质可以包括形成有长的低压氧化的隧道氧化物，并且顶部绝缘层可以包括用预热的源气体形成的二氧化硅。

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