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1. 发明授权

US08137751B2 Hierarchical structures for superhydrophobic surfaces and methods of making 有权
标题翻译：超疏水表面的分层结构和制造方法
公开(公告)号：US08137751B2
公开(公告)日：2012-03-20
申请号：US13078296
申请日：2011-04-01
申请人： Bharat Bhushan , Yong Chae Jung , Michael Nosonovsky
发明人： Bharat Bhushan , Yong Chae Jung , Michael Nosonovsky
IPC分类号： B05D1/36
CPC分类号： B32B27/08 , B05D1/60 , B05D5/08 , B05D7/02 , B08B17/06 , B08B17/065 , B32B27/06 , B32B27/283 , B32B27/38 , B32B2307/73 , Y10T428/24355 , Y10T428/24479 , Y10T428/24612 , Y10T428/24802
摘要： Embodiments of methods of making superhydrophobic structures comprise depositing a polymer mold onto a silicon surface comprising a plurality of microasperities, removing the polymer mold after the polymer mold has hardened, depositing a liquid epoxy resin into the polymer mold, forming a microstructure with a plurality of microasperities by separating the epoxy resin from the mold after the epoxy resin has solidified, and forming a superhydrophobic structure by depositing a plurality of alkane nanoasperities on the microstructure in the presence of solvent vapor.
摘要翻译：制造超疏水结构的方法的实施方案包括将聚合物模具沉积到包含多个微结构的硅表面上，在聚合物模具硬化后去除聚合物模具，将液体环氧树脂沉积到聚合物模具中，形成具有多个通过在环氧树脂固化之后将环氧树脂与模具分离，并通过在溶剂蒸气存在下在微结构上沉积多个烷烃纳米级，形成超疏水结构，从而形成微孔。

2. 发明申请

US20100028604A1 HIERARCHICAL STRUCTURES FOR SUPERHYDROPHOBIC SURFACES AND METHODS OF MAKING 审中-公开
标题翻译：超级表面的分层结构及其制造方法
公开(公告)号：US20100028604A1
公开(公告)日：2010-02-04
申请号：US12234900
申请日：2008-09-22
申请人： Bharat Bhushan , Yong Chae Jung , Michael Nosonovsky
发明人： Bharat Bhushan , Yong Chae Jung , Michael Nosonovsky
IPC分类号： B32B3/26 , B05D5/00
CPC分类号： B32B27/08 , B05D1/60 , B05D5/08 , B05D7/02 , B08B17/06 , B08B17/065 , B32B27/06 , B32B27/283 , B32B27/38 , B32B2307/73 , Y10T428/24355 , Y10T428/24479 , Y10T428/24612 , Y10T428/24802
摘要： Embodiments of a superhydrophobic structure comprise a substrate and a hierarchical surface structure disposed on at least one surface of the substrate, wherein the hierarchical surface structure comprises a microstructure comprising a plurality of microasperities disposed in a spaced geometric pattern on at least one surface of the substrate. The fraction of the surface area of the substrate covered by the microasperities is from between about 0.1 to about 1. The hierarchical structure comprises a nanostructure comprising a plurality of nanoasperities disposed on at least one surface of the microstructure.
摘要翻译：超疏水结构的实施方案包括设置在基材的至少一个表面上的基材和分层表面结构，其中分层表面结构包括微结构，其包含在基材的至少一个表面上以间隔几何图案设置的多个微孔。由微透镜覆盖的衬底的表面积的分数为约0.1至约1.层级结构包括纳米结构，其包括设置在微结构的至少一个表面上的多个纳米级。

3. 发明申请

US20110177288A1 HIERARCHICAL STRUCTURES FOR SUPERHYDROPHOBIC SURFACES AND METHODS OF MAKING 有权
标题翻译：超级表面的分层结构及其制造方法
公开(公告)号：US20110177288A1
公开(公告)日：2011-07-21
申请号：US13078296
申请日：2011-04-01
申请人： Bharat Bhushan , Yong Chae Jung , Michael Nosonovsky
发明人： Bharat Bhushan , Yong Chae Jung , Michael Nosonovsky
IPC分类号： B32B3/00 , B05D1/38
CPC分类号： B32B27/08 , B05D1/60 , B05D5/08 , B05D7/02 , B08B17/06 , B08B17/065 , B32B27/06 , B32B27/283 , B32B27/38 , B32B2307/73 , Y10T428/24355 , Y10T428/24479 , Y10T428/24612 , Y10T428/24802
摘要： Embodiments of methods of making superhydrophobic structures comprise depositing a polymer mold onto a silicon surface comprising a plurality of microasperities, removing the polymer mold after the polymer mold has hardened, depositing a liquid epoxy resin into the polymer mold, forming a microstructure with a plurality of microasperities by separating the epoxy resin from the mold after the epoxy resin has solidified, and forming a superhydrophobic structure by depositing a plurality of alkane nanoasperities on the microstructure in the presence of solvent vapor.
摘要翻译：制造超疏水结构的方法的实施方案包括将聚合物模具沉积到包含多个微结构的硅表面上，在聚合物模具硬化后去除聚合物模具，将液体环氧树脂沉积到聚合物模具中，形成具有多个通过在环氧树脂固化之后将环氧树脂与模具分离，并通过在溶剂蒸气存在下在微结构上沉积多个烷烃纳米级，形成超疏水结构，从而形成微孔。

4. 发明申请

US20060078724A1 Hydrophobic surface with geometric roughness pattern 审中-公开
标题翻译：疏水表面具有几何粗糙图案
公开(公告)号：US20060078724A1
公开(公告)日：2006-04-13
申请号：US11094867
申请日：2005-03-31
申请人： Bharat Bhushan , Michael Nosonovsky
发明人： Bharat Bhushan , Michael Nosonovsky
IPC分类号： B32B5/16
CPC分类号： B08B17/06 , B05D3/12 , B05D5/08 , B08B17/065 , Y10T428/25
摘要： A hydrophobic surface comprising a substrate and a roughened surface structure oriented on the substrate material is provided. The substrate comprises a surface, which is at least partially hydrophobic with a contact angle to liquid of 90° or greater. The roughened surface structure comprises a plurality of asperities arranged in a geometric pattern according to a roughness factor, wherein the roughness factor is characterized by a packing parameter p that equals the fraction of the surface area of the substrate covered by the asperities. The p parameter has a value from between about 0.5 to about 1.
摘要翻译：提供了一种疏水性表面，其包含基材和在该基材上取向的粗糙表面结构。衬底包括至少部分疏水的表面，其与液体的接触角为90°或更大。粗糙表面结构包括根据粗糙度因子以几何图案排列的多个凹凸，其中粗糙度因子的特征在于包装参数p等于由凹凸不平覆盖的基底的表面积的分数。 p参数具有介于约0.5至约1之间的值。

5. 发明授权

US09606926B2 System for pre-fetching data frames using hints from work queue scheduler 有权
公开(公告)号：US09606926B2
公开(公告)日：2017-03-28
申请号：US14556143
申请日：2014-11-29
申请人： Vakul Garg , Bharat Bhushan
发明人： Vakul Garg , Bharat Bhushan
IPC分类号： G06F12/00 , G06F12/0862
CPC分类号： G06F12/0862 , G06F2212/1021 , G06F2212/6028
摘要： A system for pre-fetching a data frame from a system memory to a cache memory includes a processor, a queue manager, and a pre-fetch manager. The processor issues a de-queue request associated with the data frame. The queue manager receives the de-queue request, identifies a frame descriptor associated with the data frame, and generates a pre-fetch hint signal. The pre-fetch manager receives the pre-fetch hint signal and generates a pre-fetch signal and enables the cache memory to pre-fetch the data frame. Subsequently, the queue manager de-queues the frame descriptor. The processor receives the frame descriptor and reads the data frame from the cache memory.

6. 发明申请

US20160154737A1 SYSTEM FOR PRE-FETCHING DATA FRAMES USING HINTS FROM WORK QUEUE SCHEDULER 有权
标题翻译：用于使用工作队列调度员的提示来预先切断数据框架的系统
公开(公告)号：US20160154737A1
公开(公告)日：2016-06-02
申请号：US14556143
申请日：2014-11-29
申请人： Vakul Garg , Bharat Bhushan
发明人： Vakul Garg , Bharat Bhushan
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/1021 , G06F2212/6028
摘要： A system for pre-fetching a data frame from a system memory to a cache memory includes a processor, a queue manager, and a pre-fetch manager. The processor issues a de-queue request associated with the data frame. The queue manager receives the de-queue request, identifies a frame descriptor associated with the data frame, and generates a pre-fetch hint signal. The pre-fetch manager receives the pre-fetch hint signal and generates a pre-fetch signal and enables the cache memory to pre-fetch the data frame. Subsequently, the queue manager de-queues the frame descriptor. The processor receives the frame descriptor and reads the data frame from the cache memory.
摘要翻译：用于将数据帧从系统存储器预取入高速缓冲存储器的系统包括处理器，队列管理器和预取管理器。处理器发出与数据帧相关联的解除队列请求。队列管理器接收去队列请求，识别与数据帧相关联的帧描述符，并生成预取提示信号。预取管理器接收预取提示信号并产生预取信号，并使缓存存储器能够预取数据帧。随后，队列管理器对帧描述符进行排队。处理器接收帧描述符并从高速缓冲存储器读取数据帧。

7. 发明授权

US07886238B1 Visual yield analysis of intergrated circuit layouts 有权
标题翻译：集成电路布局的视觉产量分析
公开(公告)号：US07886238B1
公开(公告)日：2011-02-08
申请号：US11564223
申请日：2006-11-28
申请人： Harsh Dev Sharma , Rajeev Srivastava , Srinivas R. Kommoori , Bharat Bhushan , Mithunjoy Parui , Albert Lee
发明人： Harsh Dev Sharma , Rajeev Srivastava , Srinivas R. Kommoori , Bharat Bhushan , Mithunjoy Parui , Albert Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Systems and methods to optimize a layout based on the yield analysis is disclosed. The method includes generating an integrated circuit layout having two or more layers of wire interconnect to form net segments and having one or more via contact layers to couple net segments in the wire interconnect together. The method further includes performing a yield analysis of the net segments in the integrated circuit layout and displaying the net segments with a visual depiction of the yield analysis using multiple levels of opacity to reflect yield scores of the net segments in the integrated circuit layout.
摘要翻译：公开了基于产量分析优化布局的系统和方法。该方法包括生成具有两层或更多层导线互连的集成电路布局，以形成网段，并且具有一个或多个通孔接触层以将导线互连中的网段耦合在一起。该方法还包括对集成电路布局中的网段执行收益率分析，并使用多个不透明度级别对收益率分析的视觉描绘来显示净段以反映集成电路布局中的网段的收益率。

8. 发明授权

US07600208B1 Automatic placement of decoupling capacitors 失效
标题翻译：自动放置去耦电容
公开(公告)号：US07600208B1
公开(公告)日：2009-10-06
申请号：US11669872
申请日：2007-01-31
申请人： Harsh Dev Sharma , Rajeev Srivastava , Srivinas R. Kommoori , Bharat Bhushan , Mithunjoy Parui , Albert Lee
发明人： Harsh Dev Sharma , Rajeev Srivastava , Srivinas R. Kommoori , Bharat Bhushan , Mithunjoy Parui , Albert Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5068
摘要： Disclosed are methods, systems and apparatus for automatically placing decoupling capacitors in an integrated circuit to compensate for voltage drops that might otherwise occur in a power grid. In one embodiment of the invention, the method includes generating one or more regions of the integrated circuit design, with each region having one or more cells, determining an amount of decoupling capacitance required in each region of the integrated circuit design by analyzing each cell in the region, and adding sufficient decoupling capacitor cells to the region to compensate for the potential voltage drop.
摘要翻译：公开了用于在集成电路中自动放置去耦电容器以补偿电网中可能出现的电压降的方法，系统和装置。在本发明的一个实施例中，该方法包括生成集成电路设计的一个或多个区域，每个区域具有一个或多个单元，通过分析集成电路设计的每个单元来确定集成电路设计的每个区域中所需的去耦电容量并且向该区域添加足够的去耦电容器单元以补偿潜在的电压降。

9. 发明授权

US07023220B2 Method for measuring nm-scale tip-sample capacitance 失效
标题翻译：测量nm尺度尖端样品电容的方法
公开(公告)号：US07023220B2
公开(公告)日：2006-04-04
申请号：US10967930
申请日：2004-10-19
申请人： Jonathan P. Pelz , David T. Lee , Bharat Bhushan
发明人： Jonathan P. Pelz , David T. Lee , Bharat Bhushan
IPC分类号： G01R27/26
CPC分类号： G01Q60/46 , G01R27/2605 , Y10S977/866
摘要： A method for measuring nm-scale tip-sample capacitance including (a) measuring a cantilever deflection and a change in probe-sample capacitance relative to a reference level as a function of a probe assembly height; (b) fitting out-of-contact data to a function; (c) subtracting the function from capacitance data to get a residual capacitance as a function of the probe assembly height; and (d) determining the residual capacitance at a z-position where the cantilever deflection is zero.
摘要翻译：一种用于测量nm尺度尖端样本电容的方法，包括（a）测量悬臂偏转和相对于参考水平的探针样品电容的变化，作为探针组件高度的函数; （b）将不合格数据拟合到一个功能上; （c）从电容数据中减去该功能，以获得作为探头组件高度的函数的残余电容; 和（d）确定悬臂偏转为零的z位置处的残余电容。

10. 发明授权

US06754689B2 Method and apparatus for performing subtraction in redundant form arithmetic 有权
标题翻译：用于以冗余形式算术进行减法的方法和装置
公开(公告)号：US06754689B2
公开(公告)日：2004-06-22
申请号：US09745697
申请日：2000-12-22
申请人： Bharat Bhushan , Edward Grochowski , John Crawford
发明人： Bharat Bhushan , Edward Grochowski , John Crawford
IPC分类号： G06F750
CPC分类号： G06F7/50 , G06F7/4824
摘要： A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in redundant form to subtract numbers received in redundant form, including numbers received from a bypass circuit. The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing an adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit to generate a valid outcome in redundant form of a subtraction operation. A carry-save adder structure is used in one preferred embodiment of the current invention to perform a subtraction operation A−B, where B is a number represented by one of its valid carry-sum redundant representations. In order to perform the subtraction operation, each of the carry bits and each of the sum bits in a redundant representation of B are complemented and supplied to the carry-save adder. Then a result is corrected by adding an adjustment of three. This adjustment value is incorporated into the result through the carry-save adder circuit. Thus the circuit produces a valid redundant representation for the subtraction operation A−B.
摘要翻译：公开了一种方法和装置，其使用运算电路来添加以冗余形式表示的数字，以减去以冗余形式接收的数字，包括从旁路电路接收的数字。该方法包括以冗余的形式生成提供给运算电路的至少一个数的补码冗余形式。它还包括向算术电路提供调整输入以增加通过算术电路产生的结果，以产生冗余形式的减法运算来产生有效结果。在本发明的一个优选实施例中使用进位保存加法器结构执行减法运算AB，其中B是由其有效进位和冗余表示之一表示的数。为了执行减法运算，B的冗余表示中的每个进位位和每个和位被补码并提供给进位存储加法器。然后通过添加三个调整来校正结果。该调整值通过进位保存加法器电路并入结果。因此，该电路产生用于减法运算A-B的有效冗余表示。

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