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1. 发明授权

US4422052A Delay circuit employing active bandpass filter 失效
标题翻译：采用有源带通滤波器的延迟电路
公开(公告)号：US4422052A
公开(公告)日：1983-12-20
申请号：US268374
申请日：1981-05-29
申请人： Bernard J. Yorkanis , Walter E. Sepp
发明人： Bernard J. Yorkanis , Walter E. Sepp
IPC分类号： H03H11/12 , H03H11/26 , H04N9/77
CPC分类号： H04N9/77 , H03H11/1213 , H03H11/26
摘要： A signal to be delayed is applied to a frequency selective path including an inverting active bandpass filter and to a non-frequency selective path including a voltage-to-current converter. The paths are coupled to a signal combiner which produces an output current having a first component proportional to the output current of the converter and a second component directly proportional to the filter output voltage and inversely proportional to the value of a gain control resistor. The resistor is selected to provide a predetermined ratio of the output current components to provide an overall allpass characteristic for the delay circuit and biased to conduct no current under quiescent signal conditions thereby reducing power dissipation. Several circuits may be cascaded for such purposes as peaking and delay equalization in television receivers, video disc players or the like.
摘要翻译：要延迟的信号被施加到包括反相有源带通滤波器的频率选择路径和包括电压 - 电流转换器的非频率选择路径。这些路径被耦合到信号组合器，该信号组合器产生具有与转换器的输出电流成比例的第一分量的输出电流和与滤波器输出电压成比例的第二分量，并与增益控制电阻器的值成反比。选择电阻器以提供输出电流分量的预定比率以提供用于延迟电路的总体全通特性，并且被偏置以在静态信号条件下不导通电流，从而降低功耗。可以将多个电路级联以用于电视接收机，视频盘播放器等中的峰化和延迟均衡。

2. 发明授权

US4277695A Amplifier having dead zone of controllable width and position 失效
标题翻译：放大器具有可控宽度和位置的死区
公开(公告)号：US4277695A
公开(公告)日：1981-07-07
申请号：US58022
申请日：1979-07-16
申请人： James A. Wilber , Bernard J. Yorkanis
发明人： James A. Wilber , Bernard J. Yorkanis
IPC分类号： H03G3/34 , G05B11/06 , G06G7/25 , H03G11/00 , H03K5/08 , H03K5/24
CPC分类号： H03G11/002 , G06G7/25
摘要： A first amplifier compares an input signal with the sum of a position control signal and a first width control signal and a second amplifier compares the position control signal with the sum of the input signal and a second width control signal, the second width control signal being derived from the same source as the first. Output circuitry combines unipolar output currents produced by the amplifiers to provide a net output current which flows in one sense to a load when the input signal is more positive than a first level and flows in the opposite sense when the input signal is more negative than a second level. No output current flows when the input signal lies within a dead zone defined by said levels, the position and width of the dead zone being separately and non-interactively controllable by said position and width signals.
摘要翻译：第一放大器将输入信号与位置控制信号和第一宽度控制信号的和进行比较，而第二放大器将位置控制信号与输入信号和第二宽度控制信号的和进行比较，第二宽度控制信号为源自与第一个相同的来源。输出电路结合由放大器产生的单极性输出电流，以提供净输出电流，当输入信号比第一电平更正时，在一个意义上流向负载，当输入信号比负电压二级当输入信号位于由所述电平限定的死区内时，没有输出电流流动，死区的位置和宽度由所述位置和宽度信号分开且不可交互地控制。

3. 发明授权

US4714871A Level shifter for a power supply regulator in a television apparatus 失效
标题翻译：电视设备中电源调节器的电平移位器
公开(公告)号：US4714871A
公开(公告)日：1987-12-22
申请号：US943187
申请日：1986-12-18
申请人： Jack Craft , Michael L. Low , Bernard J. Yorkanis
发明人： Jack Craft , Michael L. Low , Bernard J. Yorkanis
IPC分类号： H04N3/18 , G05F3/22 , G05F3/26 , G05F3/28 , H04N3/22 , H04N5/63 , G05F3/20
CPC分类号： G05F3/265 , G05F3/225 , H04N5/63
摘要： A level shifter receives a variable input voltage such as a beam current representative voltage of a cathode ray tube and produces an output voltage that changes when the input voltage changes such that the output voltage is level shifted relative to the input voltage. The output voltage is coupled to an input terminal of an error amplifier of a power supply voltage regulator of a television receiver. The level shifter includes a current mirror arrangement responsive to the input voltage. A band gap type voltage source determines the amount of level shifting that is produced by the level shifter.

4. 发明授权

US4257009A Inhibit circuit for a differential amplifier 失效
标题翻译：用于差分放大器的抑制电路
公开(公告)号：US4257009A
公开(公告)日：1981-03-17
申请号：US41752
申请日：1979-05-23
申请人： Bernard J. Yorkanis
发明人： Bernard J. Yorkanis
IPC分类号： H03G3/10 , H03F3/72 , H03F3/45
CPC分类号： H03F3/72
摘要： The outputs of a pair of non-additive combiners are coupled to respective inputs of a differential amplifier and an a.c. signal to be amplified is applied to a selected input of one of the combiners. A control circuit operates in a first mode to apply control voltages to the combiner inputs for causing the one combiner to block the a.c. signal and also causing both combiners to apply a common mode input voltage of a first value to the amplifier inputs. In a second mode, the control circuit changes the values of the control voltages in a sense to cause the one combiner to pass the a.c. signal and to also cause both combiners to apply a common mode input voltage of a second value to the amplifier inputs whereby, in either mode, the amplifier produces a constant quiescent d.c. output voltage.
摘要翻译：一对非加法组合器的输出耦合到差分放大器和交流电源的相应输入端。要被放大的信号被施加到组合器之一的所选输入端。控制电路以第一模式工作，以将组合器输入端施加控制电压，以使一个组合器阻塞一个交流电。并且还使得两个组合器将第一值的共模输入电压施加到放大器输入。在第二模式中，控制电路在某种意义上改变控制电压的值，以使一个组合器通过交流电。并且还使得两个组合器将第二值的共模输入电压施加到放大器输入，由此在任一模式中，放大器产生恒定的静态直流。输出电压。

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