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1. 发明申请

US20150140813A1 Methods of Forming Non-Volatile Memory Devices Including Vertical NAND Strings 审中-公开
标题翻译：形成包括垂直NAND串的非易失性存储器件的方法
公开(公告)号：US20150140813A1
公开(公告)日：2015-05-21
申请号：US14603827
申请日：2015-01-23
申请人： Beom-jun Jin , Byung-seo Kim , Sung-Dong Kim
发明人： Beom-jun Jin , Byung-seo Kim , Sung-Dong Kim
IPC分类号： H01L27/115 , H01L21/308
CPC分类号： H01L27/11582 , H01L21/28282 , H01L21/308 , H01L21/76802 , H01L27/11519 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11578
摘要： A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.
摘要翻译：基于NAND的非易失性存储器件可以包括垂直地布置为NAND串的多个存储单元和多个字线板，每个字线板电连接到NAND串中的存储器单元的相应栅极。多个字线触点可以各自电连接到相应的字线板，其中多个字线触点与器件中的位线方向对准。

2. 发明授权

US08971118B2 Methods of forming non-volatile memory devices including vertical NAND strings 有权
标题翻译：形成包括垂直NAND串的非易失性存储器件的方法
公开(公告)号：US08971118B2
公开(公告)日：2015-03-03
申请号：US14164712
申请日：2014-01-27
申请人： Beom-jun Jin , Byung-seo Kim , Sung-Dong Kim
发明人： Beom-jun Jin , Byung-seo Kim , Sung-Dong Kim
IPC分类号： G11C16/04 , G11C16/06 , H01L21/28 , H01L27/115 , H01L21/768
CPC分类号： H01L27/11582 , H01L21/28282 , H01L21/308 , H01L21/76802 , H01L27/11519 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11578
摘要： A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.
摘要翻译：基于NAND的非易失性存储器件可以包括垂直地布置为NAND串的多个存储单元和多个字线板，每个字线板电连接到NAND串中的存储器单元的相应栅极。多个字线触点可以各自电连接到相应的字线板，其中多个字线触点与器件中的位线方向对准。

3. 发明授权

US08325527B2 Non-volatile memory devices including vertical NAND strings and methods of forming the same 有权
标题翻译：包括垂直NAND串的非易失性存储器件及其形成方法
公开(公告)号：US08325527B2
公开(公告)日：2012-12-04
申请号：US12480399
申请日：2009-06-08
申请人： Beom-jun Jin , Byung-seo Kim , Sung-Dong Kim
发明人： Beom-jun Jin , Byung-seo Kim , Sung-Dong Kim
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： H01L27/11582 , H01L21/28282 , H01L21/308 , H01L21/76802 , H01L27/11519 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11578
摘要： A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.
摘要翻译：基于NAND的非易失性存储器件可以包括垂直地布置为NAND串的多个存储单元和多个字线板，每个字线板电连接到NAND串中的存储器单元的相应栅极。多个字线触点可以各自电连接到相应的字线板，其中多个字线触点与器件中的位线方向对准。

4. 发明申请

US20140141610A1 NON-VOLATILE MEMORY DEVICES INCLUDING VERTICAL NAND STRINGS AND METHODS OF FORMING THE SAME 有权
标题翻译：包括垂直NAND条的非易失性存储器件及其形成方法
公开(公告)号：US20140141610A1
公开(公告)日：2014-05-22
申请号：US14164712
申请日：2014-01-27
申请人： Beom-jun Jin , Byung-seo Kim , Sung-Dong Kim
发明人： Beom-jun Jin , Byung-seo Kim , Sung-Dong Kim
IPC分类号： H01L27/115 , H01L21/28
CPC分类号： H01L27/11582 , H01L21/28282 , H01L21/308 , H01L21/76802 , H01L27/11519 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11578
摘要： A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.
摘要翻译：基于NAND的非易失性存储器件可以包括垂直地布置为NAND串的多个存储单元和多个字线板，每个字线板电连接到NAND串中的存储器单元的相应栅极。多个字线触点可以各自电连接到相应的字线板，其中多个字线触点与器件中的位线方向对准。

5. 发明授权

US09373633B2 Methods of forming non-volatile memory devices including vertical NAND strings 有权
公开(公告)号：US09373633B2
公开(公告)日：2016-06-21
申请号：US14603827
申请日：2015-01-23
申请人： Beom-jun Jin , Byung-seo Kim , Sung-Dong Kim
发明人： Beom-jun Jin , Byung-seo Kim , Sung-Dong Kim
IPC分类号： H01L21/44 , H01L27/115 , H01L21/768 , H01L21/28 , H01L21/308
CPC分类号： H01L27/11582 , H01L21/28282 , H01L21/308 , H01L21/76802 , H01L27/11519 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11578
摘要： A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.

6. 发明申请

US20090310415A1 NON-VOLATILE MEMORY DEVICES INCLUDING VERTICAL NAND STRINGS AND METHODS OF FORMING THE SAME 有权
标题翻译：包括垂直NAND条的非易失性存储器件及其形成方法
公开(公告)号：US20090310415A1
公开(公告)日：2009-12-17
申请号：US12480399
申请日：2009-06-08
申请人： Beom-jun Jin , Byung-seo Kim , Sung-Dong Kim
发明人： Beom-jun Jin , Byung-seo Kim , Sung-Dong Kim
IPC分类号： G11C16/04 , H01L21/302
CPC分类号： H01L27/11582 , H01L21/28282 , H01L21/308 , H01L21/76802 , H01L27/11519 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11578
摘要： A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.
摘要翻译：基于NAND的非易失性存储器件可以包括垂直地布置为NAND串的多个存储单元和多个字线板，每个字线板电连接到NAND串中的存储器单元的相应栅极。多个字线触点可以各自电连接到相应的字线板，其中多个字线触点与器件中的位线方向对准。

7. 发明申请

US20130037946A1 SEMICONDUCTOR CHIP INCLUDING BUMP HAVING BARRIER LAYER, AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体芯片，包括带有障碍层的保护膜及其制造方法
公开(公告)号：US20130037946A1
公开(公告)日：2013-02-14
申请号：US13642713
申请日：2011-04-21
申请人： Sung-Dong Kim , Hoo-Jeong Lee , Eun-Kyung Kim , Young-Chang Joo , Gu-Sung Kim
发明人： Sung-Dong Kim , Hoo-Jeong Lee , Eun-Kyung Kim , Young-Chang Joo , Gu-Sung Kim
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/4853 , H01L23/481 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0346 , H01L2224/03462 , H01L2224/0391 , H01L2224/03912 , H01L2224/0401 , H01L2224/05009 , H01L2224/05567 , H01L2224/05568 , H01L2224/05655 , H01L2224/05666 , H01L2224/06181 , H01L2224/11009 , H01L2224/11464 , H01L2224/13025 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13166 , H01L2224/13171 , H01L2224/13181 , H01L2224/14181 , H01L2224/16148 , H01L2224/16238 , H01L2224/81193 , H01L2224/81203 , H01L2224/8181 , H01L2224/8182 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06572 , H01L2924/00014 , H01L2924/0002 , H01L2924/01029 , H01L2924/01327 , H01L2924/12042 , H01L2924/1431 , H01L2924/1434 , H01L2924/01007 , H01L2924/01028 , H01L2924/01023 , H01L2924/01074 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor chip includes a first substrate including a first surface and a second surface, a through-via plug passing through the first substrate, and a first conduction layer connected to an end of the through-via plug on the first surface, and a first bump including a first barrier layer on the first conduction layer, and a first solder layer for connecting the first substrate and a second substrate on the first barrier layer, and the first barrier layer includes a barrier material for preventing diffusion of a conductive material of the first conduction layer into the first solder layer.
摘要翻译：半导体芯片包括：第一基板，包括第一表面和第二表面;穿过第一基板的通孔塞;以及连接到第一表面上的通孔塞末端的第一导电层，包括第一导电层上的第一阻挡层的凸块和用于在第一阻挡层上连接第一基板和第二基板的第一焊料层，并且第一阻挡层包括用于防止导电材料的扩散的阻挡材料第一导电层进入第一焊料层。

8. 发明申请

US20050114016A1 Navigation system and method for updating map data based on map modification command 审中-公开
标题翻译：基于地图修改命令更新地图数据的导航系统和方法
公开(公告)号：US20050114016A1
公开(公告)日：2005-05-26
申请号：US10935604
申请日：2004-09-07
申请人： Sung-Dong Kim , Hyun-Suk Min , Sung-Chui Yang
发明人： Sung-Dong Kim , Hyun-Suk Min , Sung-Chui Yang
IPC分类号： G08G1/0968 , G01C21/20 , G01C21/32
CPC分类号： G01C21/32 , G01C21/203
摘要： A navigation system including a map data server and a navigation terminal. The map data server stores map data produced for the map information of a specific region. When an external manager modifies the map data, the server produces and transmits map modification command information corresponding to the modified map data. The navigation terminal stores map data corresponding to the map data stored in the map data server, receives and analyzes the map modification command information, and modifies the previously stored map data according to the analyzed result. Therefore, map data can be updated using the small amount of map modification command data.
摘要翻译：一种导航系统，包括地图数据服务器和导航终端。地图数据服务器存储针对特定区域的地图信息生成的地图数据。当外部管理者修改地图数据时，服务器产生并发送与修改的地图数据相对应的地图修改命令信息。导航终端存储与存储在地图数据服务器中的地图数据对应的地图数据，接收并分析地图修改命令信息，并根据分析结果修改先前存储的地图数据。因此，可以使用少量的地图修改命令数据来更新地图数据。

9. 发明申请

US20110140070A1 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHODS OF FABRICATING AND OPERATING THE SAME 审中-公开
标题翻译：三维半导体器件及其制造和操作方法
公开(公告)号：US20110140070A1
公开(公告)日：2011-06-16
申请号：US13059059
申请日：2008-09-25
申请人： Sung-Dong Kim
发明人： Sung-Dong Kim
IPC分类号： H01L27/26
CPC分类号： G11C16/0475 , G11C5/02 , G11C11/5671 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/003 , G11C16/0408 , G11C16/0483 , G11C2213/71 , G11C2213/75 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/228 , H01L27/24
摘要： Provided are three-dimensional semiconductor devices and methods of fabricating and operating the same. A device includes a connection node interposed between first and second nodes, a semiconductor pattern connected to the connection node, a plurality of memory elements connected to the semiconductor pattern, word lines connected to the memory elements, and a control electrode disposed opposite the semiconductor pattern. The control electrode selectively controls an electrical connection between the connection node and the memory element, thereby preventing an un-intended current path in a cross-point 3D memory device.
摘要翻译：提供三维半导体器件及其制造和操作的方法。一种设备包括插入在第一和第二节点之间的连接节点，连接到连接节点的半导体图案，连接到半导体图案的多个存储元件，连接到存储元件的字线以及与半导体图案相对设置的控制电极。控制电极选择性地控制连接节点和存储元件之间的电连接，从而防止交叉点3D存储器件中的未预期的电流路径。

10. 发明授权

US5799019A Circuit for converting frame data 失效
标题翻译：电路转换帧数据
公开(公告)号：US5799019A
公开(公告)日：1998-08-25
申请号：US664001
申请日：1996-06-14
申请人： Young-Goo Kim , Sung-Dong Kim
发明人： Young-Goo Kim , Sung-Dong Kim
IPC分类号： H04J3/06 , H04J3/16 , H04L29/06 , H04J3/22
CPC分类号： H04J3/1635
摘要： A circuit for converting frame data is disclosed, in which data communications can be carried out by matching the T1 repeater line of the North American method and the E1 repeater line of the CEPT. The four 32-channel frame data of the E1 line of the CEPT method are converted into parallel data of 8-bit one channel, and are stored into four 64-byte buffers. The stored 32-channel frame data are read out by 24 channels at a time, while the remaining data of the 6 channels are added to the data which have been stored in the buffers. Thus five 24-channel frame data are converted into serial data before being outputted. Of the five 24-channel frame data of the T1 repeater line of the North American method, four 24-channel frame data are stored into four 64-byte buffers, while the remaining one 24-channel frame data are separated by 6 so as to store them into the four 64-byte buffers, so that the four 64-byte buffers can store the 32-channel data respectively. The 32-channel data which have been stored in the four 64-byte buffers are sequentially read out, and then, are converted into serial data before outputting them.
摘要翻译：公开了一种用于转换帧数据的电路，其中可以通过匹配北美方法的T1中继线和CEPT的E1中继线来进行数据通信。 CEPT方法E1线的四个32通道帧数据转换为8位一个通道的并行数据，并存储在四个64字节缓冲区中。所存储的32通道帧数据一次被24个通道读出，而6个通道的剩余数据被添加到已经存储在缓冲器中的数据。因此，在输出之前，将五个24通道帧数据转换为串行数据。在北美方法的T1中继线的五个24信道帧数据中，四个24信道帧数据被存储到四个64字节缓冲器中，而剩下的一个24信道帧数据被分离为6，以便将它们存储到四个64字节缓冲区中，以便四个64字节缓冲区可以分别存储32个通道数据。已经存储在四个64字节缓冲器中的32通道数据被顺序地读出，然后在输出之前转换成串行数据。

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