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1. 发明申请

US20140285014A1 METHODS AND APPARATUS FOR A SINGLE INDUCTOR MULTIPLE OUTPUT (SIMO) DC-DC CONVERTER CIRCUIT 有权
标题翻译：单电感多输出（SIMO）DC-DC转换器电路的方法和装置
公开(公告)号：US20140285014A1
公开(公告)日：2014-09-25
申请号：US14213215
申请日：2014-03-14
申请人： Benton H. Calhoun , Aatmesh Shrivastava
发明人： Benton H. Calhoun , Aatmesh Shrivastava
IPC分类号： H02M3/158
CPC分类号： H02M3/158 , H02M2001/009 , Y10T307/406
摘要： In some embodiments, an apparatus includes a single-inductor multiple-output (SIMO) direct current (DC-DC) converter circuit, with the SIMO DC-DC converter circuit having a set of output nodes. The apparatus also includes a panoptic dynamic voltage scaling (PDVS) circuit operatively coupled to the SIMO DC-DC converter circuit, where the PDVS circuit has a set of operational blocks with each operational block from the set of operational blocks drawing power from one supply voltage rail from a set of supply voltage rails. Additionally, each output node from the set of output nodes is uniquely associated with a supply voltage rail from the set of supply voltage rails.
摘要翻译：在一些实施例中，一种装置包括单电感多输出（SIMO）直流（DC-DC）转换器电路，其中SIMO DC-DC转换器电路具有一组输出节点。该装置还包括可操作地耦合到SIMO DC-DC转换器电路的全景动态电压缩放（PDVS）电路，其中PDVS电路具有一组操作块，每个操作块与来自一个电源电压的功率块组合轨从一组供电电压轨。此外，来自该组输出节点的每个输出节点与来自该组电源电压轨的电源电压轨迹唯一地相关联。

2. 发明申请

US20150214955A1 LOW POWER CLOCK SOURCE 有权
标题翻译：低功耗时钟源
公开(公告)号：US20150214955A1
公开(公告)日：2015-07-30
申请号：US14426571
申请日：2013-09-06
申请人： Benton H. CALHOUN , Aatmesh SHRIVASTAVA
发明人： Benton H. Calhoun , Aatmesh Shrivastava
IPC分类号： H03L1/02 , H03B5/32
CPC分类号： H03L1/026 , G06F1/04 , G06F1/324 , G06F1/3287 , G06F1/3296 , H03B5/32 , H03K3/011 , H03K3/0315 , H03L1/02 , H03L1/021 , H03L1/022
摘要： An ultra-low power clock source includes a compensated oscillator and an uncompensated oscillator coupled by a comparator circuit. In an example, the compensated oscillator is more stable than the uncompensated oscillator with respect to changes in one or more of temperature, voltage, age, or other environmental parameters. The uncompensated oscillator includes a configuration input configured to adjust an operating characteristic of the uncompensated oscillator. In an example, the uncompensated oscillator is adjusted using information from the comparator circuit about a comparison of output signals from the compensated oscillator and the uncompensated oscillator.
摘要翻译：超低功率时钟源包括补偿振荡器和由比较器电路耦合的未补偿振荡器。在一个示例中，相对于温度，电压，年龄或其他环境参数中的一个或多个的变化，补偿振荡器比未补偿的振荡器更稳定。无补偿振荡器包括配置为调整未补偿振荡器的工作特性的配置输入。在一个示例中，使用来自比较器电路的信息来调整来自补偿振荡器和未补偿振荡器的输出信号的比较的未补偿振荡器。

3. 发明申请

US20130009667A1 SUB-THRESHOLD FPGA AND RELATED CIRCUITS AND METHODS THEREOF 有权
标题翻译：子阈值FPGA及其相关电路及其方法
公开(公告)号：US20130009667A1
公开(公告)日：2013-01-10
申请号：US13635350
申请日：2011-03-17
申请人： Benton H. Calhoun , Joseph F. Ryan
发明人： Benton H. Calhoun , Joseph F. Ryan
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17784 , H03K19/17788
摘要： A sub-VT FPGA uses a low swing, dual-VDD interconnect scheme to reduce FPGA area per LUT, delay at a constant energy, and energy at a constant delay relative to a conventional design at low voltage. These improvements are made possible by a custom asynchronous sense amp, a separated voltage for memory cells, and an improved passgate interconnect to optimize routing delay with low energy overhead. This sub-threshold FPGA design enables energy efficient and cost effective configurable logic for a wide variety of ULP applications.
摘要翻译：子VT FPGA采用低摆幅双VDD互连方案，以降低每个LUT的FPGA面积，以恒定能量延迟，而在低电压下相对于传统设计，能够以恒定的延迟。这些改进可以通过定制的异步感测放大器，用于存储器单元的分离电压以及改进的通道互连来实现，以优化具有低能量开销的路由延迟。该子阈值FPGA设计可为各种ULP应用提供高能效且具有成本效益的可配置逻辑。

4. 发明申请

US20150303975A1 ULTRA LOW POWER SENSING PLATFORM WITH MULTIMODAL RADIOS 有权
标题翻译：超低功率感应平台与多模式无线电
公开(公告)号：US20150303975A1
公开(公告)日：2015-10-22
申请号：US14015425
申请日：2013-08-30
申请人： Benton H. Calhoun , Yousef Shakhsheer , Yanqing Zhang , Alicia Klinefelter , David D. Wentzloff , Nathan E. Roberts , Seunghyun Oh
发明人： Benton H. Calhoun , Yousef Shakhsheer , Yanqing Zhang , Alicia Klinefelter , David D. Wentzloff , Nathan E. Roberts , Seunghyun Oh
IPC分类号： H04B1/403 , H04B1/16 , H04W4/00
CPC分类号： H04B1/406 , H04B1/1607 , H04W4/70 , Y02D70/00 , Y02D70/40
摘要： An apparatus comprises a system on a chip (SoC). In some embodiments, the SoC includes a power supply circuit, a power management circuit operatively coupled to the power supply circuit, a first wireless communications circuit and a second wireless communications circuit. The first wireless communications circuit is configured to receive an RF signal and is operatively coupled to the power supply circuit and the power management circuit. The first wireless communications circuit has a net radio frequency (RF) power gain no more than unity before at least one of downconversion of the RF signal or detection of the RF signal. The second wireless communications circuit is operatively coupled to the power supply circuit and the power management circuit.
摘要翻译：一种装置包括芯片上的系统（SoC）。在一些实施例中，SoC包括电源电路，可操作地耦合到电源电路的电源管理电路，第一无线通信电路和第二无线通信电路。第一无线通信电路被配置为接收RF信号并且可操作地耦合到电源电路和电源管理电路。第一无线通信电路在RF信号的下变频或RF信号的检测中的至少一个之前具有不大于1的净射频（RF）功率增益。第二无线通信电路可操作地耦合到电源电路和电源管理电路。

5. 发明授权

US08947912B2 Memory cell including unidirectional gate conductors and contacts 有权
标题翻译：存储单元包括单向栅极导体和触点
公开(公告)号：US08947912B2
公开(公告)日：2015-02-03
申请号：US13810728
申请日：2011-07-20
申请人： Benton H. Calhoun , Randy W. Mann
发明人： Benton H. Calhoun , Randy W. Mann
IPC分类号： G11C11/00 , H01L21/70 , G11C11/412 , H01L27/11
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/28035 , H01L21/28088 , H01L21/28097 , H01L21/768 , Y10S257/903
摘要： Memory cells are described with cross-coupled inverters including unidirectional gate conductors. Gate conductors for access transistors may also be aligned with a long axis of the inverter gate conductor. Contacts of one inverter in a cross-coupled pair may be aligned with a long axis of the other inverter's gate conductor. Separately formed rectangular active regions may be orthogonal to the gate conductors across pull up, pull down and access transistors. Separate active regions may be formed such that active regions associated with an access transistor and/or a pull up transistor are noncontiguous with, and narrower than, an active region associated with a pull down transistor of the inverter. The major components of 6T SRAM, and similar, memory cell topologies may be formed essentially from an array of rectangular lines, including unidirectional gate conductors and contacts, and unidirectional rectangular active regions crossing gate conductors of the inverters and access transistors.
摘要翻译：使用包括单向栅极导体的交叉耦合反相器来描述存储器单元。用于存取晶体管的栅极导体也可以与逆变器栅极导体的长轴对准。交叉耦合对中的一个逆变器的触点可以与另一个逆变器的栅极导体的长轴对准。单独形成的矩形有源区域可以跨越上拉，下拉和存取晶体管与栅极导体正交。可以形成单独的有源区域，使得与存取晶体管和/或上拉晶体管相关联的有源区域与与反相器的下拉晶体管相关联的有源区域不连续并且窄于与下拉晶体管的下拉晶体管相关联的有源区域。 6T SRAM和类似的存储单元拓扑的主要部件可以基本上由矩形线阵列形成，包括单向栅极导体和触点，以及与逆变器和存取晶体管交叉的栅极导体的单向矩形有源区。

6. 发明申请

US20130242645A1 Memory Cell 有权
标题翻译：内存单元
公开(公告)号：US20130242645A1
公开(公告)日：2013-09-19
申请号：US13810728
申请日：2011-07-20
申请人： Benton H. Calhoun , Randy W. Mann
发明人： Benton H. Calhoun , Randy W. Mann
IPC分类号： G11C11/412 , H01L27/11
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/28035 , H01L21/28088 , H01L21/28097 , H01L21/768 , Y10S257/903
摘要： Memory cells are described with cross-coupled inverters including unidirectional gate conductors. Gate conductors for access transistors may also be aligned with a long axis of the inverter gate conductor. Contacts of one inverter in a cross-coupled pair may be aligned with a long axis of the other inverter's gate conductor. Separately formed rectangular active regions may be orthogonal to the gate conductors across pull up, pull down and access transistors. Separate active regions may be formed such that active regions associated with an access transistor and/or a pull up transistor are noncontiguous with, and narrower than, an active region associated with a pull down transistor of the inverter. The major components of 6T SRAM, and similar, memory cell topologies may be formed essentially from an array of rectangular lines, including unidirectional gate conductors and contacts, and unidirectional rectangular active regions crossing gate conductors of the inverters and access transistors.
摘要翻译：使用包括单向栅极导体的交叉耦合反相器来描述存储器单元。用于存取晶体管的栅极导体也可以与逆变器栅极导体的长轴对准。交叉耦合对中的一个逆变器的触点可以与另一个逆变器的栅极导体的长轴对准。单独形成的矩形有源区域可以跨越上拉，下拉和存取晶体管与栅极导体正交。可以形成单独的有源区域，使得与存取晶体管和/或上拉晶体管相关联的有源区域与与反相器的下拉晶体管相关联的有源区域不连续并且窄于与下拉晶体管的下拉晶体管相关联的有源区域。 6T SRAM和类似的存储单元拓扑的主要部件可以基本上由矩形线阵列形成，包括单向栅极导体和触点，以及与反相器和存取晶体管交叉的栅极导体的单向矩形有源区。

7. 发明授权

US09729189B2 Ultra low power sensing platform with multimodal radios 有权
公开(公告)号：US09729189B2
公开(公告)日：2017-08-08
申请号：US14015425
申请日：2013-08-30
申请人： Benton H. Calhoun , Yousef Shakhsheer , Yanqing Zhang , Alicia Klinefelter , David D. Wentzloff , Nathan E. Roberts , Seunghyun Oh
发明人： Benton H. Calhoun , Yousef Shakhsheer , Yanqing Zhang , Alicia Klinefelter , David D. Wentzloff , Nathan E. Roberts , Seunghyun Oh
IPC分类号： H04B1/00 , H04B1/403 , H04B1/16 , H04W4/00
CPC分类号： H04B1/406 , H04B1/1607 , H04W4/70 , Y02D70/00 , Y02D70/40
摘要： An apparatus comprises a system on a chip (SoC). In some embodiments, the SoC includes a power supply circuit, a power management circuit operatively coupled to the power supply circuit, a first wireless communications circuit and a second wireless communications circuit. The first wireless communications circuit is configured to receive an RF signal and is operatively coupled to the power supply circuit and the power management circuit. The first wireless communications circuit has a net radio frequency (RF) power gain no more than unity before at least one of downconversion of the RF signal or detection of the RF signal. The second wireless communications circuit is operatively coupled to the power supply circuit and the power management circuit.

8. 发明授权

US09178518B2 Sub-threshold FPGA and related circuits and methods thereof 有权
标题翻译：子阈值FPGA及其相关电路及其方法
公开(公告)号：US09178518B2
公开(公告)日：2015-11-03
申请号：US13635350
申请日：2011-03-17
申请人： Benton H. Calhoun , Joseph F. Ryan
发明人： Benton H. Calhoun , Joseph F. Ryan
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17784 , H03K19/17788
摘要： A sub-VT FPGA uses a low swing, dual-VDD interconnect scheme to reduce FPGA area per LUT, delay at a constant energy, and energy at a constant delay relative to a conventional design at low voltage. These improvements are made possible by a custom asynchronous sense amp, a separated voltage for memory cells, and an improved passgate interconnect to optimize routing delay with low energy overhead. This sub-threshold FPGA design enables energy efficient and cost effective configurable logic for a wide variety of ULP applications.
摘要翻译：子VT FPGA采用低摆幅双VDD互连方案，以降低每个LUT的FPGA面积，以恒定能量延迟，而在低电压下相对于传统设计，能够以恒定的延迟。这些改进可以通过定制的异步感测放大器，用于存储器单元的分离电压以及改进的通道互连来实现，以优化具有低能量开销的路由延迟。该子阈值FPGA设计可为各种ULP应用提供高能效且具有成本效益的可配置逻辑。

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