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    • 4. 发明授权
    • Method and circuit for increasing the memory access speed of an enhanced synchronous SDRAM
    • 提高增强型同步SDRAM存储器访问速度的方法和电路
    • US06813679B2
    • 2004-11-02
    • US10178072
    • 2002-06-20
    • Kenneth J. MobleyMichael T. PetersMichael Schuette
    • Kenneth J. MobleyMichael T. PetersMichael Schuette
    • G06F1208
    • G11C11/4097G06F12/0893G06F2212/3042G11C2207/2245
    • An SDRAM and method for operating it provide for increased data access speed. The SDRAM includes a central memory region with memory blocks arranged in sets on respective opposite sides. A plurality of primary sense amplifier sets are provided, each set being associated with a respective set of the memory blocks and located adjacent thereto. A row cache is provided in the central memory region, and row decoders decode a row address in response to a “bank activate” command and move data from a decoded row address into a primary sense amplifier set associated with a memory block containing the decoded row address and into the row cache, prior to application of a “read” command to the SDRAM. Column decoders decode a column address in response to a “read” command and for reading data from the cache in accordance with the decoded column address.
    • 用于操作它的SDRAM和方法提供了增加的数据访问速度。 SDRAM包括具有在相应相对侧上以集合排列的存储块的中央存储器区域。 提供了多个原始感测放大器组,每组都与相应的存储器组的集合相关联,并位于其附近。 在中央存储器区域中提供行缓存,并且行解码器响应于“存储体激活”命令对行地址进行解码,并将数据从解码的行地址移动到与包含解码行的存储器块相关联的初级读出放大器组 地址和行缓存之前,应用一个“读”命令到SDRAM。 列解码器响应于“读取”命令解码列地址,并根据解码的列地址从高速缓存读取数据。
    • 6. 发明授权
    • Method and circuit for increasing the memory access speed of an enhanced synchronous memory
    • 用于增加增强型同步存储器的存储器存取速度的方法和电路
    • US07533231B1
    • 2009-05-12
    • US10965602
    • 2004-10-13
    • Kenneth J. MobleyMichael T. PetersMichael Schuette
    • Kenneth J. MobleyMichael T. PetersMichael Schuette
    • G06F13/14
    • G11C11/4097G06F12/0893G06F2212/3042G11C2207/2245
    • A memory and method for operating it provide for increased data access speed. In an implementation, a synchronous memory or SDRAM includes a central memory region with memory blocks arranged in sets on respective opposite sides. A number of primary sense amplifier sets are provided, each set being associated with a respective set of the memory blocks and located adjacent. A row cache is provided in the central memory region, and row decoders decode a row address in response to a “bank activate” command and move data from a decoded row address into a primary sense amplifier set associated with a memory block containing the decoded row address and into the row cache, before application of a “read” command to the SDRAM. Column decoders decode a column address in response to a “read” command and for reading data from the cache in accordance with the decoded column address.
    • 用于操作它的存储器和方法提供了增加的数据访问速度。 在一个实现中,同步存储器或SDRAM包括具有在相应相对侧上以集合排列的存储器块的中央存储器区域。 提供了许多初级感测放大器组,每组都与相应的存储块集合相关联并且位于相邻的位置。 在中央存储器区域中提供行缓存,并且行解码器响应于“存储体激活”命令对行地址进行解码,并将数据从解码的行地址移动到与包含解码行的存储器块相关联的初级读出放大器组 地址并进入行缓存,然后将“读”命令应用于SDRAM。 列解码器响应于“读取”命令解码列地址,并根据解码的列地址从高速缓存读取数据。
    • 7. 发明授权
    • Adjustable-height vertical gel slab electrophoresis apparatus
    • 可调高度立式凝胶电泳仪
    • US4957613A
    • 1990-09-18
    • US248196
    • 1988-09-23
    • Michael Schuette
    • Michael Schuette
    • G01N27/447
    • G01N27/44756G01N27/44704
    • An adjustable-height vertical gel slab electrophoresis apparatus comprises a vertically oriented gel slab arranged between upper and lower buffer solution reservoirs. A bifurcated removable lower tray contains both an upper buffer reservoir drain and lower buffer reservoir. A gel mold experiment can be assembled and disassembled with unusual ease with the aid of unique self-locking clamp assemblies. Modular units may be vertically stacked to construct a vertical electrophoresis apparatus of variable height. Separable but interlocking upper and lower portions of the adjustable-height apparatus may have inserted between them intermediate insert assemblies which effectively extend the vertical height of the apparatus, thus facilitating flexibility in performing electrophoresis runs of greatly varying physical length without the need to purchase entirely separate units of different heights. Various interlocking wobble or tilt in either vertical plane. Means for stabilizing the apparatus in a true vertical position are also provided.
    • 可调高度的垂直凝胶板电泳装置包括布置在上下缓冲液储存器之间的垂直取向的凝胶板。 分叉可拆卸的下部托盘包含上部缓冲储存器排水和下部缓冲储存器。 借助于独特的自锁夹具组件,凝胶模具实验可以非常容易地组装和拆卸。 模块化单元可以垂直堆叠构成可变高度的垂直电泳装置。 可调高度装置的可分离但互锁的上部和下部可以插入在它们之间的中间插入组件中,这有效地延长了装置的垂直高度,因此有助于进行大大变化的物理长度的电泳运行的灵活性,而不需要完全分开购买 不同高度的单位。 在垂直平面内各种互锁摆动或倾斜。 还提供了用于在真实垂直位置稳定装置的装置。
    • 9. 发明申请
    • HYDRAULIC FAN DRIVE
    • 液压风扇驱动
    • US20130202452A1
    • 2013-08-08
    • US13638016
    • 2011-03-03
    • Michael SchuetteTobias PfruenderMartin FassbenderEgon Rill
    • Michael SchuetteTobias PfruenderMartin FassbenderEgon Rill
    • F04D13/04
    • F04D13/046F01P7/044
    • A hydraulic fan drive includes a hydraulic pump that has an adjustable swept volume. The hydraulic pump is assigned a pressure control valve arrangement that is configured to regulate a pump pressure by adjustment of the swept volume. The drive further includes a hydraulic motor configured to drive an impeller wheel and a pressure line, which is connected to a pressure input of the hydraulic motor and into which pressure medium is configured to be conveyed by the hydraulic pump. A hydraulic accumulator is connected to the pressure line and the displacement of the hydraulic motor is configured to be adjusted. Energy is buffer-stored by the hydraulic accumulator by feeding in pressure medium beyond the amount that is displaced by the hydraulic motor. This stored energy becomes free for other operations of a machine, for example, to which the drive is attached.
    • 液压风扇驱动器包括具有可调节的扫掠体积的液压泵。 液压泵被分配有压力控制阀装置,其配置成通过调节扫掠体积来调节泵的压力。 驱动装置还包括液压马达,该液压马达构造成驱动叶轮和压力线,该叶轮和压力线连接到液压马达的压力输入端,压力介质构造成由液压泵输送。 液压蓄能器与压力线连接,液压马达的排量被调整。 通过在压力介质中进给超过液压马达所移动量的液体蓄能器来缓冲储存能量。 这种存储的能量对于机器的其他操作变得免费,例如,驱动器附接到机器。
    • 10. 发明申请
    • Memory address generation with non-harmonic indexing
    • 具有非谐波索引的存储器地址生成
    • US20070083729A1
    • 2007-04-12
    • US11247425
    • 2005-10-11
    • Kent MoatRaymond EssickMichael Schuette
    • Kent MoatRaymond EssickMichael Schuette
    • G06F12/00
    • G06F9/345G06F9/3455
    • A method for generating a sequence of memory addresses for a multi-dimensional data structure and an address generation unit are disclosed. The address generation unit includes an ADDRESS register, a STRIDE register, and a plurality skip generators, each having SKIP, SPAN and COUNT registers. An address value is initialized to a first address and each COUNT register is initialized. For each address of the sequence an address value is output and a stride value is added to the address value. For each dimension of the data structure the COUNT register associated with the dimension is updated as each address is generated. For all dimensions, when the COUNT register value becomes zero, the skip value associated with the dimension is added to the address value and its COUNT register is reset to a specified value.
    • 公开了一种用于生成多维数据结构和地址生成单元的存储器地址序列的方法。 地址生成单元包括地址寄存器,STRIDE寄存器和多个跳过发生器,每个具有SKIP,SPAN和COUNT寄存器。 地址值被初始化为第一个地址,并且每个COUNT寄存器被初始化。 对于序列的每个地址,输出地址值,并将stride值添加到地址值。 对于数据结构的每个维度,与维度相关联的COUNT寄存器随着生成每个地址而被更新。 对于所有维度,当COUNT寄存器值为零时,与维度相关联的跳过值将添加到地址值,并将其COUNT寄存器重置为指定值。