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    • 1. 发明授权
    • Voltage controlled oscillator
    • 压控振荡器
    • US07961057B2
    • 2011-06-14
    • US12200009
    • 2008-08-28
    • Beng Hwee OngMinjie WuWee Liang LienChang-Fu Kuo
    • Beng Hwee OngMinjie WuWee Liang LienChang-Fu Kuo
    • H03B19/12
    • H03L7/099H03B5/1215H03B5/1228H03B5/1243
    • An integrated circuit and an apparatus are provided. The integrated circuit comprises a bias circuit, an LC resonator circuit, and a current mode logic (CML) frequency divider. The bias circuit generates first and second bias voltages. The LC resonator circuit generates an oscillation signal having an oscillation frequency. The CML frequency divider, coupled to the bias circuit and the LC resonator circuit, biased by the first and second bias voltages, receives the oscillation signal to generate an output signal having an output frequency with a fractional rate of the oscillation frequency. The oscillation signal comprises AC and DC components, the CML frequency divider receives the AC component to determine an injected frequency and reuses the DC component to provide tail currents to determine a natural frequency of the CML frequency divider. The output frequency is determined by the injected frequency and the natural frequency.
    • 提供集成电路和装置。 集成电路包括偏置电路,LC谐振电路和电流模式逻辑(CML)分频器。 偏置电路产生第一和第二偏置电压。 LC谐振器电路产生具有振荡频率的振荡信号。 耦合到偏置电路和LC谐振器电路的由第一和第二偏置电压偏置的CML分频器接收振荡信号以产生具有振荡频率的分数速率的输出频率的输出信号。 振荡信号包括AC和DC分量,CML分频器接收AC分量以确定注入频率,并重新使用DC分量来提供尾电流以确定CML分频器的固有频率。 输出频率由注入频率和固有频率决定。
    • 2. 发明授权
    • High-speed phase frequency detection module
    • 高速相频检测模块
    • US06778026B2
    • 2004-08-17
    • US10053480
    • 2002-01-15
    • Jonathon CheahChristopher YongMinjie Wu
    • Jonathon CheahChristopher YongMinjie Wu
    • H03L700
    • H03D13/004H03L7/0896H03L7/18
    • A high-speed phase-frequency detection module is described to function at very high frequencies and to produce very low jitter. In one embodiment, high-speed phase-frequency detection module includes a PFD with edge-triggered asynchronous-reset true-single-phase-clocking (“TSPC”) D flip-flops that have very short CLK to Q and Reset to Q time delays. In one embodiment, the high-speed phase-frequency detection module includes a charge pump, without replica or feedback, that can respond to the very narrow pulses from the PFD and produce output voltages with small ripple, thus leading to low VCO output jitter.
    • 高速相位频率检测模块被描述为在非常高的频率下工作并产生非常低的抖动。 在一个实施例中,高速相位频率检测模块包括具有边沿触发异步复位的真 - 单相时钟(“TSPC”)D触发器的PFD,其具有非常短的CLK到Q和复位到Q时间 延误 在一个实施例中,高速相位频率检测模块包括无需复制或反馈的电荷泵,其可响应来自PFD的非常窄的脉冲并产生具有小纹波的输出电压,从而导致低VCO输出抖动。