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1. 发明授权

US5646450A Semiconductor structures and method of manufacturing 失效
标题翻译：半导体结构及制造方法
公开(公告)号：US5646450A
公开(公告)日：1997-07-08
申请号：US594511
申请日：1996-01-31
申请人： Barry J. Liles , Mark S. Durschlag , James G. Oakes
发明人： Barry J. Liles , Mark S. Durschlag , James G. Oakes
IPC分类号： H01L23/482 , H01L23/66 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/4821 , H01L23/66 , H01L2924/0002
摘要： A semiconductor structure is described having a first electrode and a second electrode disposed on a surface of the structure and a bridging conductor connected between the first electrode and the second electrode. The bridging conductor includes a plurality of layers of different metals wherein the plurality of layers of different metals includes a layer of refractory metal adjacent a layer of electrically conductive metal. In a preferred embodiment, the refractory metal is titanium and the electrically conductive metal is gold. With such an arrangement, a semiconductor structure is provided which is effective in preventing restructuring due to mechanical stresses induced in the metal by dissimilar thermal expansion coefficients when electrical pulsing cycles the temperature of the semiconductor structure.
摘要翻译：描述了半导体结构，其具有设置在该结构的表面上的第一电极和第二电极以及连接在第一电极和第二电极之间的桥接导体。桥接导体包括多个不同金属的层，其中不同金属的多个层包括与导电金属层相邻的难熔金属层。在优选的实施方案中，难熔金属是钛，导电金属是金。通过这样的布置，提供半导体结构，其有效地防止了当电脉冲循环半导体结构的温度时，通过不同的热膨胀系数在金属中引起的机械应力来防止重构。

2. 发明授权

US4927784A Simultaneous formation of via hole and tube structures for GaAs monolithic microwave integrated circuits 失效
标题翻译：同时形成GaAs单片微波集成电路的通孔和管结构
公开(公告)号：US4927784A
公开(公告)日：1990-05-22
申请号：US250207
申请日：1988-09-28
申请人： Thomas E. Kazior , Mark S. Durschlag
发明人： Thomas E. Kazior , Mark S. Durschlag
IPC分类号： H01L21/388 , H01L21/74 , H01L23/36 , H01L23/48 , H01L23/528
CPC分类号： H01L21/388 , H01L21/743 , H01L23/36 , H01L23/481 , H01L23/5283 , H01L2224/04026 , H01L2924/10158 , H01L2924/12032 , H01L2924/3011
摘要： A method of simultaneously forming recesses for via holes and tube structures in a substrate is provided in a common etching step by defining a mask pattern for the via hole as a single aperture and by defining a mask pattern for the tub structure as a plurality of thin slots. The slots are chosen to have a smaller cross-sectional dimension than the corresponding dimension for the single aperture. Etchant brought into contact with the substrate will etch the substrate at a slower rate in the slots than in the single aperture such that the via hole will etch completely through the substrate whereas, the tub structure will be etched only partially through the substrate. Conductive material is provided in the tub structure and via hole, and a layer of conductive material is disposed thereover, to provide a heat sink/ground plane conductor. Electrical contact is provided between the frontside of the substrate and the heat sink/ground plane conductor through the via hole, whereas a low thermal impedance path is provided through the tub structure between a heat dissipating element supported on the frontside of the substrate and the heat sink/ground plane conductor.
摘要翻译：在通常的蚀刻步骤中，通过将通孔的掩模图案定义为单个孔，并且通过将用于桶结构的掩模图案限定为多个薄的方法，来提供同时形成衬底中的通孔和管结构的凹槽的方法插槽狭槽被选择为具有比单个孔径的相应尺寸更小的横截面尺寸。与衬底接触的蚀刻剂将在槽中以比在单个孔中更慢的速率蚀刻衬底，使得通孔将完全蚀刻通过衬底，而桶结构将仅部分地通过衬底被蚀刻。导电材料设置在桶结构和通孔中，并且在其上设置一层导电材料，以提供散热器/接地面导体。在基板的前侧和通过通孔的散热器/接地面导体之间提供电接触，而在支撑在基板的前侧的散热元件和热量之间通过槽结构提供低热阻抗路径接收/接地平面导体。

3. 发明授权

US4807022A Simultaneous formation of via hole and tub structures for GaAs monolithic microwave integrated circuits 失效
标题翻译：同时形成GaAs单片微波集成电路的通孔和槽结构
公开(公告)号：US4807022A
公开(公告)日：1989-02-21
申请号：US044684
申请日：1987-05-01
申请人： Thomas E. Kazior , Mark S. Durschlag
发明人： Thomas E. Kazior , Mark S. Durschlag
IPC分类号： H01L21/388 , H01L21/74 , H01L23/36 , H01L23/48 , H01L23/528 , H01L23/34 , H01L21/302 , H01L27/04
CPC分类号： H01L21/743 , H01L21/388 , H01L23/36 , H01L23/481 , H01L23/5283 , H01L2924/0002 , H01L2924/10158 , H01L2924/3011
摘要： A method of simultaneously forming recesses for via holes and tub structures in a substrate is provided in a common etching step by defining a mask pattern for the via hole as a single aperture and by defining a mask pattern for the tub structure as a plurality of thin slots. The slots are chosen to have a smaller cross-sectional dimension than the corresponding dimension for the single aperture. Etchant brought into contact with the substrate will etch the substrate at a slower rate in the slots than in the single apertur such that the via hole will etch completely through the substrate whereas, the tub structure will be etched only partially through the substrate. Conductive material is provided in the tub structure and via hole, and a layer of conductive material is disposed thereover, to provide a heat sink/ ground plane conductor. Electrical contact is provided between the frontside of the substrate and the heat sink/ground plane conductor through the via hole, whereas a low thermal impedance path is provided through the tube structure between a heat dissipating element supported on the frontside of the substrate and the heat sink/ground plane conductor.
摘要翻译：在通常的蚀刻步骤中，通过将通孔的掩模图案定义为单个孔，并且通过将用于桶结构的掩模图案限定为多个薄的方法，来提供在衬底中同时形成通孔和桶结构的凹槽的方法插槽狭槽被选择为具有比单个孔径的相应尺寸更小的横截面尺寸。与衬底接触的蚀刻剂将在槽中以比单个孔中更慢的速率蚀刻衬底，使得通孔将完全蚀刻通过衬底，而桶结构将仅部分地蚀刻通过衬底。导电材料设置在桶结构和通孔中，并且在其上设置一层导电材料，以提供散热器/接地面导体。在基板的前侧和通过通孔的散热器/接地平面导体之间提供电接触，而在基板的前侧支撑的散热元件和热量之间通过管结构提供低热阻抗路径接收/接地平面导体。

4. 发明授权

US4670297A Evaporated thick metal and airbridge interconnects and method of manufacture 失效
标题翻译：蒸发厚金属和气桥互连及制造方法
公开(公告)号：US4670297A
公开(公告)日：1987-06-02
申请号：US747518
申请日：1985-06-21
申请人： Kyu-Woong Lee , Mark S. Durschlag , John Day
发明人： Kyu-Woong Lee , Mark S. Durschlag , John Day
IPC分类号： H01L21/027 , H01L21/28 , H01L21/768 , H01L23/482 , H01L23/52 , H01L21/88 , H01L21/312
CPC分类号： H01L21/28 , H01L21/0272 , H01L21/7688 , H01L21/76885 , H01L23/4821 , H01L23/52 , H01L2924/0002
摘要： A first masking layer of a first resist is provided over a semiconductor substrate and is patterned in a selected region to provide a masked region over which an airbridge interconnect will be provided. A second relatively thick layer of a second, different type of resist and a third relatively thin layer of resist are provided, respectively, over the substrate. The second and third layers of resist are patterned to provide an aperture having overhanging portions exposing the previously applied patterned regions of the first layer, and selected adjacent portions of the substrate. The second and third layers may also be patterned to provide a region for a patterned strip conductor. A stream of evaporated metal is directed towards the substrate and deposited within the apertures to provide an airbridge interconnect conductor and patterned strip conductor. The overhanging portions of the apertures provide separation between the metal layer deposited within the aperture and the metal layer deposited over the third masking layer, allowing the second and third masking layers to be lifted-off without disturbing the conductors. The masked regions underlying the bridges are also removed leaving the airbridge interconnect and patterned strip conductor.
摘要翻译：第一抗蚀剂的第一掩蔽层设置在半导体衬底上并且在选定的区域中被图案化以提供掩蔽区域，在该掩模区域将提供空中桥互连。在基板上分别设置第二相对较厚的第二不同类型的抗蚀剂层和第三相对较薄的抗蚀剂层。将第二层和第三层抗蚀剂图案化以提供具有突出部分的孔，其暴露先前施加的第一层的图案化区域和基板的相邻部分。第二层和第三层也可以被图案化以提供用于图案化带状导体的区域。蒸发的金属流指向基板并沉积在孔内，以提供空中桥互连导体和图案化的带状导体。孔的突出部分提供了沉积在孔内的金属层与沉积在第三掩模层上的金属层之间的分离，允许第二和第三掩蔽层被提起而不干扰导体。桥下面的掩蔽区域也被去除，留下了空中桥互连和图案化的带状导体。

5. 发明授权

US4458295A Lumped passive components and method of manufacture 失效
标题翻译：集中无源元件及制造方法
公开(公告)号：US4458295A
公开(公告)日：1984-07-03
申请号：US440479
申请日：1982-11-09
申请人： Mark S. Durschlag , James L. Vorhaus
发明人： Mark S. Durschlag , James L. Vorhaus
IPC分类号： H01L27/04 , H01G4/08 , H01G4/10 , H01G9/00 , H01L21/316 , H01L21/70 , H01L21/822 , H01G7/00 , H01L27/02
CPC分类号： H01L21/707 , H01G4/08 , H01G4/10 , H01L28/40 , Y10T29/435
摘要： Lumped passive components including a capacitor having a silicon nitride dielectric, a tantalum film resistor, and a capacitor having a tantalum oxide dielectric are formed on a semi-insulating substrate by first providing an insulating layer, here of silicon nitride, over the substrate and metal contacts having previously been formed on such substrate. The metal contacts provide a first plate for each one of such capacitors. A tantalum layer is reactively sputtered on the insulating layer, and a protective masking layer is next provided on such tantalum layer. An area where the anodized tantalum capacitor is to be formed is then opened in the protective masking layer over a selected one of the metal contacts. A portion of the tantalum is anodized in such area to form an area of a tantalum oxide (Ta.sub.2 O.sub.5). The area where the tantalum oxide is formed is confined generally to the area in the tantalum layer over the contact. The masking layer is removed and a second masking layer is patterned to provide an etching mask used to etch the tantalum layer to define each one of such capacitors, and to provide a strip of tantalum, defining a region for said tantalum resistor. Top metal contacts are then provided aligned with the first set of such contacts, and thus providing a second metal plate of the anodized tantalum capacitor and a second metal plate of the silicon nitride capacitor. Further, a set of metal contacts is provided to each end of the tantalum strip to provide the tantalum resistor.
摘要翻译：通过在衬底和金属上首先提供绝缘层（这里是氮化硅），在半绝缘衬底上形成包括具有氮化硅电介质的电容器，钽膜电阻器和具有氧化钽电介质的电容器的集总无源部件先前已经形成在这种基板上的触点。金属触点为每个这种电容器提供第一板。在绝缘层上反应溅射钽层，然后在该钽层上设置保护掩模层。然后在所选择的一个金属触点上的保护掩模层中打开要形成阳极氧化的钽电容器的区域。钽的一部分在这样的区域被阳极氧化以形成氧化钽（Ta 2 O 5）的面积。形成氧化钽的区域通常限定在接触层上的钽层中的区域。去除掩模层，并且对第二掩模层进行图案化，以提供用于蚀刻钽层的蚀刻掩模，以限定这些电容器中的每一个，并提供限定用于所述钽电阻器的区域的钽带。然后将顶部金属触点设置成与第一组这样的触点对齐，从而提供阳极化钽电容器的第二金属板和氮化硅电容器的第二金属板。此外，在钽带的每一端提供一组金属触点，以提供钽电阻。

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