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1. 发明授权

US08134209B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08134209B2
公开(公告)日：2012-03-13
申请号：US12640658
申请日：2009-12-17
申请人： Atsushi Yagishita , Makoto Fujiwara , Hirohisa Kawasaki , Mariko Takayanagi
发明人： Atsushi Yagishita , Makoto Fujiwara , Hirohisa Kawasaki , Mariko Takayanagi
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： Multi-gate metal oxide silicon transistors and methods of making multi-gate metal oxide silicon transistors are provided. The multi-gate metal oxide silicon transistor contains a bulk silicon substrate containing one or more convex portions between shallow trench regions; one or more dielectric portions over the convex portions; one or more silicon fins over the dielectric portions; a shallow trench isolation layer in the shallow trench isolation regions; and a gate electrode. The upper surface of the shallow trench isolation layer can be located below the upper surface of the convex portion, or the upper surface of the shallow trench isolation layer can be located between the lower surface and the upper surface of first dielectric layer. The multi-gate metal oxide silicon transistor can contain second spacers adjacent to side surfaces of the convex portions in a source/drain region.
摘要翻译：提供多栅极金属氧化物硅晶体管和制造多栅极金属氧化物硅晶体管的方法。多栅极金属氧化物硅晶体管包含在浅沟槽区域之间包含一个或多个凸部的体硅衬底; 一个或多个在凸部上的电介质部分; 电介质部分上的一个或多个硅散热片; 在浅沟槽隔离区域的浅沟槽隔离层; 和栅电极。浅沟槽隔离层的上表面可以位于凸部的上表面下方，或者浅沟槽隔离层的上表面可以位于第一介电层的下表面和上表面之间。多栅极金属氧化物硅晶体管可以包含与源极/漏极区域中的凸部的侧表面相邻的第二间隔物。

2. 发明申请

US20110147839A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110147839A1
公开(公告)日：2011-06-23
申请号：US12640658
申请日：2009-12-17
申请人： Atsushi Yagishita , Makoto Fujiwara , Hirohisa Kawasaki , Mariko Takayanagi
发明人： Atsushi Yagishita , Makoto Fujiwara , Hirohisa Kawasaki , Mariko Takayanagi
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： Multi-gate metal oxide silicon transistors and methods of making multi-gate metal oxide silicon transistors are provided. The multi-gate metal oxide silicon transistor contains a bulk silicon substrate containing one or more convex portions between shallow trench regions; one or more dielectric portions over the convex portions; one or more silicon fins over the dielectric portions; a shallow trench isolation layer in the shallow trench isolation regions; and a gate electrode. The upper surface of the shallow trench isolation layer can be located below the upper surface of the convex portion, or the upper surface of the shallow trench isolation layer can be located between the lower surface and the upper surface of first dielectric layer. The multi-gate metal oxide silicon transistor can contain second spacers adjacent to side surfaces of the convex portions in a source/drain region.
摘要翻译：提供多栅极金属氧化物硅晶体管和制造多栅极金属氧化物硅晶体管的方法。多栅极金属氧化物硅晶体管包含在浅沟槽区域之间包含一个或多个凸部的体硅衬底; 一个或多个在凸部上的电介质部分; 电介质部分上的一个或多个硅散热片; 在浅沟槽隔离区域的浅沟槽隔离层; 和栅电极。浅沟槽隔离层的上表面可以位于凸部的上表面下方，或者浅沟槽隔离层的上表面可以位于第一介电层的下表面和上表面之间。多栅极金属氧化物硅晶体管可以包含与源极/漏极区域中的凸部的侧表面相邻的第二间隔物。

3. 发明申请

US20090174036A1 PLASMA CURING OF PATTERNING MATERIALS FOR AGGRESSIVELY SCALED FEATURES 审中-公开
标题翻译：等离子体固化材料的等离子体刻蚀特性
公开(公告)号：US20090174036A1
公开(公告)日：2009-07-09
申请号：US11969525
申请日：2008-01-04
申请人： Nicholas C. Fuller , Michael A. Guillorn , Hirohisa Kawasaki , Atsushi Yagishita
发明人： Nicholas C. Fuller , Michael A. Guillorn , Hirohisa Kawasaki , Atsushi Yagishita
IPC分类号： H01L29/30 , G03F7/26
CPC分类号： G03F7/40
摘要： A methodology is disclosed that enables the fabrication of semiconductor devices (i.e., STI structures, gates, and interconnects) with significantly reduced line edge roughness (LER) and line width roughness (LEW) post lithography patterning. The inventive methodology entails the use of an inert species containing plasma tuned to enhanced its' vacuum ultra violet (VUV) emissions post lithography and/or post one of the etch processes of a given feature (on an identical etch platform) to entice increased crosslinking of one or more patterning materials, thus enabling increased etch resistance and reduced LER and LEW post etching processing.
摘要翻译：公开了一种能够在光刻图案化之后显着降低线边缘粗糙度（LER）和线宽粗糙度（LEW）来制造半导体器件（即STI结构，栅极和互连）的方法。本发明的方法需要使用含有等离子体的惰性物质来调整光刻后的真空紫外（VUV）发射和/或给定特征（在相同的蚀刻平台上）的一个蚀刻工艺，以引发增加的交联的一个或多个图案形成材料，因此能够提高耐蚀刻性和减少LER和LEW后蚀刻处理。

4. 发明申请

US20120049281A1 SEMICONDUCTOR DEVICE WITH EFFECTIVE WORK FUNCTION CONTROLLED METAL GATE 审中-公开
标题翻译：具有有效工作功能的半导体器件控制金属栅
公开(公告)号：US20120049281A1
公开(公告)日：2012-03-01
申请号：US12870011
申请日：2010-08-27
申请人： Yoshinori Tsuchiya , Ryosuke Iijima , Atsushi Yagishita
发明人： Yoshinori Tsuchiya , Ryosuke Iijima , Atsushi Yagishita
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L29/785 , H01L29/66795
摘要： According to one embodiment, gate electrodes of a multi-gate field effect transistors and methods of making a gate electrode of a multi-gate field effect transistor are provided. The gate electrode can contain a semiconductor substrate; a dielectric layer over the semiconductor substrate; a fin over the dielectric layer; a gate insulating layer over the side surfaces of the fin; a gate electrode layer over the fin; and a polysilicon layer over the fin. The gate electrode does not contain a gate insulating layer over the upper surface of the dielectric layer except portions of the upper surface of the dielectric layer that contact with the side surfaces of the gate insulating layer formed over the side surface of the fin. In another embodiment, the gate electrode can contain an oxygen diffusion barrier layer or a first oxygen diffusion layer over the upper surface of the dielectric layer.
摘要翻译：根据一个实施例，提供了多栅极场效应晶体管的栅极和制造多栅极场效应晶体管的栅电极的方法。栅电极可以包含半导体衬底; 半导体衬底上的电介质层; 电介质层上的翅片; 在翅片的侧表面上的栅极绝缘层; 翅片上的栅极电极层; 和鳍上的多晶硅层。栅电极除电介质层上表面的与栅极侧表面上形成的栅极绝缘层的侧面接触的部分以外，在电介质层的上表面上不包含栅极绝缘层。在另一个实施例中，栅电极可以在电介质层的上表面上包含氧扩散阻挡层或第一氧扩散层。

5. 发明授权

US08053292B2 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08053292B2
公开(公告)日：2011-11-08
申请号：US12805533
申请日：2010-08-04
申请人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
发明人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
IPC分类号： H01L21/8238
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/045 , H01L29/6681 , H01L29/7843
摘要： The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.
摘要翻译：本公开涉及一种制造半导体器件的方法，包括在绝缘层上形成由半导体材料制成的多个鳍片; 在所述多个翅片的侧面上形成栅极绝缘膜; 以及在所述栅极绝缘膜上形成栅电极，使得在与所述侧面垂直的方向上在所述多个翅片中的NMOSFET中使用的第一鳍片的侧面施加压缩应力，在垂直于侧面的方向上，在多个翅片中的PMOSFET中使用的第二鳍片的侧面施加应力。

6. 发明授权

US07723171B2 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07723171B2
公开(公告)日：2010-05-25
申请号：US12078585
申请日：2008-04-02
申请人： Atsushi Yagishita , Akio Kaneko , Kazunari Ishimaru
发明人： Atsushi Yagishita , Akio Kaneko , Kazunari Ishimaru
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/28097 , H01L21/823431 , H01L27/0886 , H01L29/66795 , H01L29/6681 , H01L29/7851
摘要： According to the present invention, there is provided a semiconductor device fabrication method, comprising:depositing a mask material on a semiconductor substrate;patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region;burying a device isolation insulating film in the trench;etching away a predetermined amount of the device isolation insulating film formed in the first region;etching away the mask material formed in the second region;forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection;depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film;planarizing the first gate electrode material by using as stoppers the mask material formed in the first region and the device isolation insulating film formed in the second region;depositing a second gate electrode material on the mask material, first gate electrode material, and device isolation insulating film; andpatterning the first and second gate electrode materials, thereby forming a first gate electrode in the first region, and a second gate electrode in the second region.
摘要翻译：根据本发明，提供了一种半导体器件制造方法，包括：在半导体衬底上沉积掩模材料; 图案化掩模材料并通过蚀刻在半导体衬底的表面部分中形成沟槽，从而在第一区域中形成第一突起，在第二区域形成比第一突起宽的第二突起; 在沟槽中埋设器件隔离绝缘膜; 蚀刻形成在第一区域中的预定量的器件隔离绝缘膜; 蚀刻形成在第二区域中的掩模材料; 在所述第一突起的一对相对的侧面上形成第一栅极绝缘膜，在所述第二突起的上表面上形成第二栅极绝缘膜; 在器件隔离绝缘膜，掩模材料和第二栅极绝缘膜上沉积第一栅电极材料; 通过使用形成在第一区域中的掩模材料和形成在第二区域中的器件隔离绝缘膜作为阻挡层来平坦化第一栅电极材料; 在掩模材料上沉积第二栅电极材料，第一栅电极材料和器件隔离绝缘膜; 以及对第一和第二栅电极材料进行构图，从而在第一区域形成第一栅电极，在第二区域形成第二栅电极。

7. 发明申请

US20100081240A1 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100081240A1
公开(公告)日：2010-04-01
申请号：US12585554
申请日：2009-09-17
申请人： Atsushi Yagishita
发明人： Atsushi Yagishita
IPC分类号： H01L21/86
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/41791 , H01L29/66795 , H01L29/785 , H01L2029/7858
摘要： A method of manufacturing a semiconductor device includes forming a plurality of Fins including a semiconductor material on an insulation layer; forming gate insulation films on sidewalls of the Fins; forming a gate electrode which extends in a direction of arrangement of the Fins and which is electrically insulated from the Fins, the gate electrode is common in the Fins on the gate insulation film; implanting an impurity into portions of the Fins by using the gate electrode as a mask to form a source-drain diffusion layer, the portions of the Fins extending on both sides of the gate electrodes; and depositing a conductive material on both sides of the Fins to connect the Fins to each other.
摘要翻译：制造半导体器件的方法包括在绝缘层上形成包括半导体材料的多个金属丝; 在金属丝的侧壁上形成栅极绝缘膜; 形成栅极电极，所述栅电极在所述鳍片的布置方向上延伸并且与所述鳍状物电绝缘，所述栅极电极在所述栅极绝缘膜上的所述鳍片中是共同的; 通过使用栅极电极作为掩模将杂质注入到薄片的部分中以形成源极 - 漏极扩散层，鳍状物的部分在栅电极的两侧延伸; 以及在所述金属丝的两侧上沉积导电材料以将所述金属丝彼此连接。

8. 发明授权

US07537978B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07537978B2
公开(公告)日：2009-05-26
申请号：US11717068
申请日：2007-03-13
申请人： Atsushi Yagishita , Ichiro Mizushima , Tsutomu Sato
发明人： Atsushi Yagishita , Ichiro Mizushima , Tsutomu Sato
IPC分类号： H01L21/00
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/66545 , H01L29/78639 , H01L29/78648
摘要： A semiconductor device comprises a support layer made of semiconductor, a diffusion layer formed by implanting impurities in a surface layer of the support layer, a buried insulating layer provided on the diffusion layer, an island-like active layer provided on the buried insulating layer, a channel region formed in the active layer, source and drain regions formed in the active layer, sandwiching the channel region, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film and on side surfaces of the island-like active layer, and insulated and isolated from the channel, source, and drain regions, and an electrode connected to the active layer.
摘要翻译：半导体器件包括由半导体制成的支撑层，通过在支撑层的表面层中注入杂质形成的扩散层，设置在扩散层上的掩埋绝缘层，设置在掩埋绝缘层上的岛状有源层，形成在有源层中的沟道区域，形成在有源层中的源极和漏极区域，夹持沟道区域，形成在沟道区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极和岛的侧表面类型的有源层，并且与沟道，源极和漏极区域绝缘和隔离，以及连接到有源层的电极。

9. 发明申请

US20070099385A1 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20070099385A1
公开(公告)日：2007-05-03
申请号：US11540708
申请日：2006-10-02
申请人： Kazuaki Nakajima , Atsushi Yagishita
发明人： Kazuaki Nakajima , Atsushi Yagishita
IPC分类号： H01L21/336
CPC分类号： H01L21/823835 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method of manufacturing a semiconductor device, comprising forming an electrode pattern made of silicon on a gate insulating film in an n-MOS region and a p-MOS region of a semiconductor substrate, masking the n-MOS region including the first electrode pattern with a first insulating film pattern, forming a first metal film made of platinum all over the surface, forming a gate electrode consisting of a platinum silicide in the p-MOS region, forming an silicon oxide film on the surface of the gate electrode by oxidation, dissolving away a non-reacting Pt film, removing the first insulating film pattern, masking the p-MOS region including the electrode pattern with a second insulating film pattern, forming a second metal film made of europium all over the surface, and forming a gate electrode consisting of a europium silicide in the n-MOS region.
摘要翻译：本发明提供一种制造半导体器件的方法，包括在n-MOS区的栅极绝缘膜和半导体衬底的p-MOS区中形成由硅制成的电极图案，掩蔽包括具有第一绝缘膜图案的第一电极图案，在整个表面上形成由铂制成的第一金属膜，在p-MOS区中形成由铂硅化物组成的栅电极，在栅极的表面上形成氧化硅膜电极通过氧化，去除不反应的Pt膜，去除第一绝缘膜图案，用第二绝缘膜图案掩蔽包括电极图案的p-MOS区，在整个表面上形成由铕制成的第二金属膜，以及在n-MOS区中形成由硅化铕构成的栅电极。

10. 发明授权

US06815279B2 Manufacturing method of CMOS devices 有权
标题翻译： CMOS器件的制造方法
公开(公告)号：US06815279B2
公开(公告)日：2004-11-09
申请号：US09907952
申请日：2001-07-19
申请人： Atsushi Yagishita , Kouji Matsuo
发明人： Atsushi Yagishita , Kouji Matsuo
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/26506 , H01L21/823807 , H01L21/823828 , H01L29/1054
摘要： A semiconductor device in which an NMOSFET and a PMOSFET are formed in a silicon substrate, wherein the gate electrodes of NMOSFET and PMOSFET are made of metallic materials, an Si—Ge layer is formed in at least part of the surface regions including the respective channel layers of the NMOSFET and PMOSFET, and the concentration of Ge in the channel layer of the NMOSFET is lower than the concentration of Ge in the channel layer of the PMOSFET.

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