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    • 3. 发明授权
    • Encoding device and decoding device
    • 编码设备和解码设备
    • US08429503B2
    • 2013-04-23
    • US12671188
    • 2008-07-29
    • Shutai OkamuraMasayuki OrihashiAtsushi Sumasu
    • Shutai OkamuraMasayuki OrihashiAtsushi Sumasu
    • H03M13/00
    • H03M13/1128H03M13/1102H03M13/1105H03M13/27H03M13/373H03M13/6356H03M13/6362H03M13/6516H04L1/0041H04L1/005H04L1/0057H04L1/0071
    • Disclosed are an encoding device and a decoding device which can effectively reduce the decoding failure frequency in LDPC encoding/decoding. A loss correction encoding device (120) includes a padding unit (121) which adds a padding packet to an information packet sequence; an interleave unit (122) which rearranges the padding packet and the information packet; and a loss correction encoding unit (123) which performs loss correction encoding for the packet string after the interleave. The interleave unit (122) rearranges the padding packet and the information packet according to variable nodes constituting a minimum stopping set of the inspection matrix which defines a low-density parity inspection code. The interleave unit (122) uses such a rearrangement pattern that avoids a loss correction failure by the minimum stopping set of the LDPC inspection matrix so as to reduce the probability of the loss correction failure by the minimum stopping set.
    • 公开了可以有效地降低LDPC编码/解码中的解码失败频率的编码装置和解码装置。 丢失校正编码装置(120)包括将填充分组添加到信息分组序列的填补单元(121) 交织单元(122),其重新排列所述填充分组和所述信息分组; 以及丢失校正编码单元(123),其在交织之后对分组串执行丢失校正编码。 交错单元(122)根据构成检查矩阵的最小停止集合的可变节点重新排列填充分组和信息分组,该检查矩阵定义了低密度奇偶校验检验码。 交错单元(122)使用这样的重排模式,通过LDPC检查矩阵的最小停止集合来避免丢失校正失败,从而通过最小停止集合来降低丢失校正失败的可能性。
    • 4. 发明申请
    • ENCODING DEVICE AND DECODING DEVICE
    • 编码设备和解码设备
    • US20100218066A1
    • 2010-08-26
    • US12671188
    • 2008-07-29
    • Shutai OkamuraMasayuki OrihashiAtsushi Sumasu
    • Shutai OkamuraMasayuki OrihashiAtsushi Sumasu
    • H03M13/27G06F11/10
    • H03M13/1128H03M13/1102H03M13/1105H03M13/27H03M13/373H03M13/6356H03M13/6362H03M13/6516H04L1/0041H04L1/005H04L1/0057H04L1/0071
    • Disclosed are an encoding device and a decoding device which can effectively reduce the decoding failure frequency in LDPC encoding/decoding. A loss correction encoding device (120) includes a padding unit (121) which adds a padding packet to an information packet sequence; an interleave unit (122) which rearranges the padding packet and the information packet; and a loss correction encoding unit (123) which performs loss correction encoding for the packet string after the interleave. The interleave unit (122) rearranges the padding packet and the information packet according to variable nodes constituting a minimum stopping set of the inspection matrix which defines a low-density parity inspection code. The interleave unit (122) uses such a rearrangement pattern that avoids a loss correction failure by the minimum stopping set of the LDPC inspection matrix so as to reduce the probability of the loss correction failure by the minimum stopping set.
    • 公开了可以有效地降低LDPC编码/解码中的解码失败频率的编码装置和解码装置。 丢失校正编码装置(120)包括将填充分组添加到信息分组序列的填补单元(121) 交织单元(122),其重新排列所述填充分组和所述信息分组; 以及丢失校正编码单元(123),其在交织之后对分组串执行丢失校正编码。 交错单元(122)根据构成检查矩阵的最小停止集合的可变节点重新排列填充分组和信息分组,该检查矩阵定义了低密度奇偶校验检验码。 交错单元(122)使用这样的重排模式,通过LDPC检查矩阵的最小停止集合来避免丢失校正失败,从而通过最小停止集合来降低丢失校正失败的可能性。
    • 6. 发明授权
    • Encoder, decoder, encoding method, and decoding method
    • 编码器,解码器,编码方法和解码方法
    • US08458577B2
    • 2013-06-04
    • US12745216
    • 2008-12-18
    • Shutai OkamuraYutaka MurakamiMasayuki Orihashi
    • Shutai OkamuraYutaka MurakamiMasayuki Orihashi
    • G06F11/00
    • H03M13/255H03M13/1128H03M13/116H03M13/118H03M13/23H03M13/6362H03M13/6502H03M13/6527
    • There is provided an encoder that provides a termination sequence with a simple structure for LDPC-CC encoding and reduces an amount of the termination sequence transmitted to a transmission line. The LDPC-CC encoder (200) connects a first encoder (230) to a second encoder (240) to perform encoding and thereby carry out LDPC-CC encoding, the first encoder (230) performing encoding based on an partial parity check matrix for information bits (110) obtained by extracting a sequence corresponding to the information bits in a parity check matrix (100) and the second encoder (240) performing encoding based on a partial parity check matrix for parity bits (120) obtained by extracting a sequence corresponding to the parity bits in the parity check matrix (100). A termination sequence generator (210) generates a termination sequence including the same number of bits as the memory length of the first encoder (230) and provides the generated termination sequence as an input sequence.
    • 提供了一种编码器,其提供具有用于LDPC-CC编码的简单结构的终止序列,并减少发送到传输线的终止序列的量。 LDPC-CC编码器(200)将第一编码器(230)连接到第二编码器(240)以执行编码,从而执行LDPC-CC编码,第一编码器(230)基于部分奇偶校验矩阵执行编码, 通过提取与奇偶校验矩阵(100)中的信息比特相对应的序列获得的信息比特(110)和基于通过提取序列获得的奇偶校验比特(120)的部分奇偶校验矩阵执行编码的第二编码器(240) 对应于奇偶校验矩阵(100)中的奇偶校验位。 终止序列生成器(210)生成包括与第一编码器(230)的存储器长度相同数量的位的终止序列,并且将生成的终止序列提供为输入序列。
    • 9. 发明授权
    • MIMO receiver and MIMO communication system
    • MIMO接收机和MIMO通信系统
    • US08229016B2
    • 2012-07-24
    • US12294804
    • 2007-03-30
    • Shutai OkamuraMasayuki OrihashiTakaaki KishigamiYutaka Murakami
    • Shutai OkamuraMasayuki OrihashiTakaaki KishigamiYutaka Murakami
    • H04L27/28H04L27/06
    • H04B7/04H04B7/0697H04B7/0854H04L1/0625H04L1/0631H04L1/0643
    • An MIMO receiver and MIMO communication system which can have a small hardware scale even if the number of antennas used for MIMO communication. In a radio communication device (200), a receiving section (220) receives a spatially multiplexed signal generated by mutually-different and spatially multiplexing transmission signals, a first signal demultiplexing section (230) subjects a linear operation to the received spatial multiplexed signal to demultiplex the spatial multiplexed signal, and a second signal demultiplexing section (240) demultiplexer the demultiplexed spatially multiplexed signal into the transmission signals. When the received signal is demultiplexed by a single demultiplexing, as the number of multiplexed spatial multiplexed signal increases, the demultiplexer becomes complicated, and the hardware scale increases. When the received signal is demultiplexed by a plurality of demultiplexings, the hardware scale is relatively small.
    • 即使用于MIMO通信的天线数量,MIMO接收机和MIMO通信系统也可以具有小的硬件规模。 在无线通信装置(200)中,接收部(220)接收通过相互不同的空间复用的发送信号生成的空间复用信号,第一信号解复用部(230)对所接收的空间复用信号进行线性运算 解复用空间多路复用信号,第二信号解复用部分(240)将解复用的空间多路复用信号解复用为传输信号。 当接收到的信号被单解复用解复用时,随着多路复用信号的复用信号数量的增加,解复用器变得复杂,硬件规模增大。 当接收到的信号被多路解复用时,硬件比例相对较小。
    • 10. 发明申请
    • LOW-DENSITY PARITY CHECK CONVOLUTION CODE (LDPC-CC) ENCODER AND LDPC-CC DECODER
    • 低密度奇偶校验调制码(LDPC-CC)编码器和LDPC-CC解码器
    • US20100199153A1
    • 2010-08-05
    • US12668655
    • 2008-07-11
    • Shutai OkamuraYutaka MurakamiMasayuki Orihashi
    • Shutai OkamuraYutaka MurakamiMasayuki Orihashi
    • H03M13/15G06F11/10
    • H03M13/118H03M13/1111H03M13/1154H03M13/23H03M13/235H03M13/6362
    • It is possible to provide and an LDPC-CC (Low-Density Parity-Check Convolution Codes) encoder and an LDPC-CC decoder which performs an error correction encoding and decoding while reducing the amount of a termination sequence required for encoding/decoding the LDPC-CC encoding/decoding and suppressing degradation of the transmission efficiency. The LDPC-CC encoder (400) includes a weight control unit (470) which stores a weight pattern (475) based on an LDPC-CC inspection matrix (100); and a weight pattern (476) based on a check matrix (300) obtained by deforming an LDPC-CC inspection matrix (100). The weight control unit (470) controls a weight to be multiplied onto the outputs of a plurality of shift registers (410-1 to 410-M, 430-1 to 430-M) by using the weight pattern (475) when the input bit is an information sequence, and using a weight pattern (476) which makes a weight value to be multiplied by an inspection bit v2,t to be 0 when the input bit is a termination sequence.
    • 可以提供LDPC-CC(低密度奇偶校验卷积码)编码器和LDPC-CC解码器,该LDPC-CC解码器在减少LDPC编码/解码所需的终止序列的量的同时进行纠错编码和解码 -CC编码/解码并抑制传输效率的降低。 LDPC-CC编码器(400)包括:权重控制单元(470),其基于LDPC-CC检查矩阵(100)存储权重模式(475); 以及基于通过使LDPC-CC检查矩阵(100)变形而获得的校验矩阵(300)的权重模式(476)。 权重控制单元(470)通过使用加权模式(475)来控制要乘以多个移位寄存器(410-1至410-M,430-1至430-M)的输出的权重 位是信息序列,并且当输入比特是终止序列时,使用使加权值乘以检查比特v2的加权模式(476),t为0。