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    • 1. 发明授权
    • Low-density parity check convolution code (LDPC-CC) encoder and LDPC-CC decoder
    • 低密度奇偶校验卷积码(LDPC-CC)编码器和LDPC-CC解码器
    • US08423876B2
    • 2013-04-16
    • US12668655
    • 2008-07-11
    • Shutai OkamuraYutaka MurakamiMasayuki Orihashi
    • Shutai OkamuraYutaka MurakamiMasayuki Orihashi
    • H03M13/03
    • H03M13/118H03M13/1111H03M13/1154H03M13/23H03M13/235H03M13/6362
    • It is possible to provide and an LDPC-CC (Low-Density Parity-Check Convolution Codes) encoder and an LDPC-CC decoder which performs an error correction encoding and decoding while reducing the amount of a termination sequence required for encoding/decoding the LDPC-CC encoding/decoding and suppressing degradation of the transmission efficiency. The LDPC-CC encoder (400) includes a weight control unit (470) which stores a weight pattern (475) based on an LDPC-CC inspection matrix (100); and a weight pattern (476) based on a check matrix (300) obtained by deforming an LDPC-CC inspection matrix (100). The weight control unit (470) controls a weight to be multiplied onto the outputs of a plurality of shift registers (410-1 to 410-M, 430-1 to 430-M) by using the weight pattern (475) when the input bit is an information sequence, and using a weight pattern (476) which makes a weight value to be multiplied by an inspection bit v2,t to be 0 when the input bit is a termination sequence.
    • 可以提供LDPC-CC(低密度奇偶校验卷积码)编码器和LDPC-CC解码器,该LDPC-CC解码器在减少LDPC编码/解码所需的终止序列的量的同时进行纠错编码和解码 -CC编码/解码并抑制传输效率的降低。 LDPC-CC编码器(400)包括:权重控制单元(470),其基于LDPC-CC检查矩阵(100)存储权重模式(475); 以及基于通过使LDPC-CC检查矩阵(100)变形而获得的校验矩阵(300)的权重模式(476)。 权重控制单元(470)通过使用加权模式(475)来控制要乘以多个移位寄存器(410-1至410-M,430-1至430-M)的输出的权重 位是信息序列,并且当输入比特是终止序列时,使用使加权值乘以检查比特v2的加权模式(476),t为0。
    • 5. 发明申请
    • ENCODER, DECODER, ENCODING METHOD, AND DECODING METHOD
    • 编码器,解码器,编码方法和解码方法
    • US20100269009A1
    • 2010-10-21
    • US12745216
    • 2008-12-18
    • Shutai OkamuraYutaka MurakamiMasayuki Orihashi
    • Shutai OkamuraYutaka MurakamiMasayuki Orihashi
    • H03M13/05G06F11/10
    • H03M13/255H03M13/1128H03M13/116H03M13/118H03M13/23H03M13/6362H03M13/6502H03M13/6527
    • There is provided an encoder that provides a termination sequence with a simple structure for LDPC-CC encoding and reduces an amount of the termination sequence transmitted to a transmission line. The LDPC-CC encoder (200) connects a first encoder (230) to a second encoder (240) to perform encoding and thereby carry out LDPC-CC encoding, the first encoder (230) performing encoding based on an partial parity check matrix for information bits (110) obtained by extracting a sequence corresponding to the information bits in a parity check matrix (100) and the second encoder (240) performing encoding based on a partial parity check matrix for parity bits (120) obtained by extracting a sequence corresponding to the parity bits in the parity check matrix (100). A termination sequence generator (210) generates a termination sequence including the same number of bits as the memory length of the first encoder (230) and provides the generated termination sequence as an input sequence.
    • 提供了一种编码器,其提供具有用于LDPC-CC编码的简单结构的终止序列,并减少发送到传输线的终止序列的量。 LDPC-CC编码器(200)将第一编码器(230)连接到第二编码器(240)以执行编码,从而执行LDPC-CC编码,第一编码器(230)基于部分奇偶校验矩阵执行编码, 通过提取与奇偶校验矩阵(100)中的信息比特相对应的序列获得的信息比特(110)和基于通过提取序列获得的奇偶校验比特(120)的部分奇偶校验矩阵执行编码的第二编码器(240) 对应于奇偶校验矩阵(100)中的奇偶校验位。 终止序列生成器(210)生成包括与第一编码器(230)的存储器长度相同数量的位的终止序列,并且将生成的终止序列提供为输入序列。
    • 6. 发明申请
    • TRANSMITTING DEVICE AND TRANSMITTING METHOD
    • 发送设备和发送方法
    • US20100192047A1
    • 2010-07-29
    • US12668829
    • 2008-07-11
    • Yutaka MurakamiShutai OkamuraMasayuki Orihashi
    • Yutaka MurakamiShutai OkamuraMasayuki Orihashi
    • H03M13/03G06F11/00
    • H04L1/0057H03M13/1111H03M13/235H03M13/2707H03M13/353H03M13/6306H04L1/0059H04L1/1812H04L5/0007H04L5/0042
    • A transmitting device and method enabling improvement of the reception quality on the receiving side when the LDPC-CC (Low-Density Parity-Check Convolutional Codes) encoding is used. The transmitting device (100) comprises an LDPC-CC encoding section (102), a sorting section (121) for sorting the encoded data (120) acquired by the LDPC-CC encoding section (102) into a first encoded data set (103_A) corresponding to the column number of the column containing “1” in a part of an LDPC-CC check matrix H from which a protograph is excluded and a second encoded data set (103_B) corresponding to the column numbers of the columns other than that, and a frame constructing section (a control section (106)) for constructing a transmission frame where the first and second encoded data sets (103_A, 103_B) are arranged in positions different in time or frequency in the transmission frame.
    • 当使用LDPC-CC(低密度奇偶校验卷积码)编码时,能够提高接收侧的接收质量的发送装置和方法。 发送设备(100)包括LDPC-CC编码部分(102),用于将由LDPC-CC编码部分(102)获取的编码数据(120)分类为第一编码数据集(103_A)的排序部分 )对应于从其排除原型图的LDPC-CC校验矩阵H的一部分中包含“1”的列的列号,以及对应于除此之外的列的列号的第二编码数据集(103_B) ,以及用于构造传输帧的帧构造部(控制部(106)),其中第一和第二编码数据集(103_A,103_B)被布置在传输帧中的时间或频率不同的位置。
    • 7. 发明申请
    • MIMO RECEIVER AND MIMO COMMUNICATION SYSTEM
    • MIMO接收机和MIMO通信系统
    • US20100172421A1
    • 2010-07-08
    • US12294804
    • 2007-03-30
    • Shutai OkamuraMasayuki OrihashiTakaaki KishigamiYutaka Murakami
    • Shutai OkamuraMasayuki OrihashiTakaaki KishigamiYutaka Murakami
    • H04L27/28H04L27/06
    • H04B7/04H04B7/0697H04B7/0854H04L1/0625H04L1/0631H04L1/0643
    • An MIMO receiver and MIMO communication system which can have a small hardware scale even if the number of antennas used for MIMO communication. In a radio communication device (200), a receiving section (220) receives a spatially multiplexed signal generated by mutually-different and spatially multiplexing transmission signals, a first signal demultiplexing section (230) subjects a linear operation to the received spatial multiplexed signal to demultiplex the spatial multiplexed signal, and a second signal demultiplexing section (240) demultiplexer the demultiplexed spatially multiplexed signal into the transmission signals. When the received signal is demultiplexed by a single demultiplexing, as the number of multiplexed spatial multiplexed signal increases, the demultiplexer becomes complicated, and the hardware scale increases. When the received signal is demultiplexed by a plurality of demultiplexings, the hardware scale is relatively small.
    • 即使用于MIMO通信的天线数量,MIMO接收机和MIMO通信系统也可以具有小的硬件规模。 在无线通信装置(200)中,接收部(220)接收通过相互不同的空间复用的发送信号生成的空间复用信号,第一信号解复用部(230)对所接收的空间复用信号进行线性运算 解复用空间多路复用信号,第二信号解复用部分(240)将解复用的空间多路复用信号解复用为传输信号。 当接收到的信号被单解复用解复用时,随着多路复用信号的复用信号数量的增加,解复用器变得复杂,硬件规模增大。 当接收到的信号被多路解复用时,硬件比例相对较小。
    • 9. 发明授权
    • Encoder, decoder, encoding method, and decoding method
    • 编码器,解码器,编码方法和解码方法
    • US08458577B2
    • 2013-06-04
    • US12745216
    • 2008-12-18
    • Shutai OkamuraYutaka MurakamiMasayuki Orihashi
    • Shutai OkamuraYutaka MurakamiMasayuki Orihashi
    • G06F11/00
    • H03M13/255H03M13/1128H03M13/116H03M13/118H03M13/23H03M13/6362H03M13/6502H03M13/6527
    • There is provided an encoder that provides a termination sequence with a simple structure for LDPC-CC encoding and reduces an amount of the termination sequence transmitted to a transmission line. The LDPC-CC encoder (200) connects a first encoder (230) to a second encoder (240) to perform encoding and thereby carry out LDPC-CC encoding, the first encoder (230) performing encoding based on an partial parity check matrix for information bits (110) obtained by extracting a sequence corresponding to the information bits in a parity check matrix (100) and the second encoder (240) performing encoding based on a partial parity check matrix for parity bits (120) obtained by extracting a sequence corresponding to the parity bits in the parity check matrix (100). A termination sequence generator (210) generates a termination sequence including the same number of bits as the memory length of the first encoder (230) and provides the generated termination sequence as an input sequence.
    • 提供了一种编码器,其提供具有用于LDPC-CC编码的简单结构的终止序列,并减少发送到传输线的终止序列的量。 LDPC-CC编码器(200)将第一编码器(230)连接到第二编码器(240)以执行编码,从而执行LDPC-CC编码,第一编码器(230)基于部分奇偶校验矩阵执行编码, 通过提取与奇偶校验矩阵(100)中的信息比特相对应的序列获得的信息比特(110)和基于通过提取序列获得的奇偶校验比特(120)的部分奇偶校验矩阵执行编码的第二编码器(240) 对应于奇偶校验矩阵(100)中的奇偶校验位。 终止序列生成器(210)生成包括与第一编码器(230)的存储器长度相同数量的位的终止序列,并且将生成的终止序列提供为输入序列。