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1. 发明授权

US07064988B2 Synchronous semiconductor memory device of fast random cycle system and test method thereof 失效
标题翻译：快速随机循环系统的同步半导体存储器件及其测试方法
公开(公告)号：US07064988B2
公开(公告)日：2006-06-20
申请号：US11244606
申请日：2005-10-05
申请人： Kazuko Inuzuka , Kazuaki Kawaguchi
发明人： Kazuko Inuzuka , Kazuaki Kawaguchi
IPC分类号： G11C7/00 , G11C8/00 , G11C8/18
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C11/401 , G11C11/4076 , G11C29/12015 , G11C29/14 , G11C29/46 , G11C29/48
摘要： An FCRAM includes first to third circuits. The first circuit generates a first signal based on a command detection signal. The second circuit is configured to receive the command detection signal, an operation mode specifying signal and a selection signal and generate a second signal which causes the start timing of the operation of a row-system circuit to be synchronized with the input timing of a second command. The third circuit is configured to select the first signal when a normal operation mode is specified by the operation mode specifying signal, select the second signal when a test mode is specified, and generate a third signal used to activate at least part of the memory cells in a memory cell array based on a selected one of the first and second signals and the selection signal.
摘要翻译： FCRAM包括第一至第三电路。第一电路基于命令检测信号产生第一信号。第二电路被配置为接收命令检测信号，操作模式指定信号和选择信号，并且生成使行系统电路的操作的开始定时与第二信号的输入定时同步的第二信号命令。第三电路被配置为当通过操作模式指定信号指定正常操作模式时选择第一信号，当指定测试模式时选择第二信号，并且生成用于激活至少部分存储器单元的第三信号在基于第一和第二信号中选择的一个和选择信号的存储单元阵列中。

2. 发明申请

US20060028885A1 Synchronous semiconductor memory device of fast random cycle system and test method thereof 失效
公开(公告)号：US20060028885A1
公开(公告)日：2006-02-09
申请号：US11244597
申请日：2005-10-05
申请人： Kazuko Inuzuka , Kazuaki Kawaguchi
发明人： Kazuko Inuzuka , Kazuaki Kawaguchi
IPC分类号： G11C7/00
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C11/401 , G11C11/4076 , G11C29/12015 , G11C29/14 , G11C29/46 , G11C29/48
摘要： An FCRAM includes first to third circuits. The first circuit generates a first signal based on a command detection signal. The second circuit is configured to receive the command detection signal, an operation mode specifying signal and a selection signal and generate a second signal which causes the start timing of the operation of a row-system circuit to be synchronized with the input timing of a second command. The third circuit is configured to select the first signal when a normal operation mode is specified by the operation mode specifying signal, select the second signal when a test mode is specified, and generate a third signal used to activate at least part of the memory cells in a memory cell array based on a selected one of the first and second signals and the selection signal.

3. 发明授权

US07102959B2 Synchronous semiconductor memory device of fast random cycle system and test method thereof 失效
公开(公告)号：US07102959B2
公开(公告)日：2006-09-05
申请号：US11244597
申请日：2005-10-05
申请人： Kazuko Inuzuka , Kazuaki Kawaguchi
发明人： Kazuko Inuzuka , Kazuaki Kawaguchi
IPC分类号： G11C8/00 , G11C8/18 , G11C7/00
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C11/401 , G11C11/4076 , G11C29/12015 , G11C29/14 , G11C29/46 , G11C29/48
摘要： An FCRAM includes first to third circuits. The first circuit generates a first signal based on a command detection signal. The second circuit is configured to receive the command detection signal, an operation mode specifying signal and a selection signal and generate a second signal which causes the start timing of the operation of a row-system circuit to be synchronized with the input timing of a second command. The third circuit is configured to select the first signal when a normal operation mode is specified by the operation mode specifying signal, select the second signal when a test mode is specified, and generate a third signal used to activate at least part of the memory cells in a memory cell array based on a selected one of the first and second signals and the selection signal.

4. 发明授权

US06226204B1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06226204B1
公开(公告)日：2001-05-01
申请号：US09141450
申请日：1998-08-27
申请人： Kazuko Inuzuka , Katsushi Nagaba , Shigeo Ohshima
发明人： Kazuko Inuzuka , Katsushi Nagaba , Shigeo Ohshima
IPC分类号： G11C1604
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： The data output circuit in a clock synchronous DRAM comprises a first data transfer circuit to which the data read from a memory is input and which transfers the input data to the output side in synchronization with an internal clock, an equalizing circuit to which the output of the first data transfer circuit is input during a read operation by a burst operation and to which high-impedance data is input after the read operation, a second data transfer circuit connected to the equalizing circuit, and an output buffer to which the output of the second data transfer circuit is input. The second data transfer circuit transfers all the data to the output buffer in synchronization with an output clock. This eliminates the dependence of the data access time and data hold time on data item and/or cycle and facilitates the timing control of the output control signal.
摘要翻译：时钟同步DRAM中的数据输出电路包括第一数据传输电路，从存储器读取的数据被输入到该第一数据传输电路，并且将输入数据与内部时钟同步地传送到输出端;均衡电路，第一数据传送电路在读操作期间通过脉冲串操作输入，并且在读操作之后输入高阻数据，连接到均衡电路的第二数据传输电路和输出缓冲器第二数据传输电路被输入。第二数据传输电路与输出时钟同步地将所有数据传送到输出缓冲器。这消除了数据访问时间和数据保持时间对数据项和/或周期的依赖性，并且便于输出控制信号的定时控制。

5. 发明授权

US5777946A Semiconductor memory circuit equipped with a column addressing circuit having a shift register 失效
标题翻译：配备有具有移位寄存器的列寻址电路的半导体存储器电路
公开(公告)号：US5777946A
公开(公告)日：1998-07-07
申请号：US770404
申请日：1996-12-20
申请人： Kazuko Inuzuka , Shigeo Ohshima , Katsushi Nagaba
发明人： Kazuko Inuzuka , Shigeo Ohshima , Katsushi Nagaba
IPC分类号： G11C11/407 , G11C8/04 , G11C11/408
CPC分类号： G11C8/04
摘要： The present invention provides a semiconductor memory circuit capable of high-speed access to a predetermined column portion by a simplified high-speed addressing circuit. The memory circuit in a DRAM is such that a portion of a column addressing circuit normally comprising a counter constitutes a shift register in a column addressing circuit at a preceding stage of a column address buffer so that a plurality of address signal wrappings are realized for accessing the predetermined column portion.
摘要翻译：本发明提供一种能够通过简化的高速寻址电路高速访问预定列部分的半导体存储器电路。 DRAM中的存储器电路使得通常包括计数器的列寻址电路的一部分在列地址缓冲器的前级构成列寻址电路中的移位寄存器，从而实现多个地址信号包装以进行访问预定列部分。

6. 发明授权

US06973000B2 Synchronous semiconductor memory device of fast random cycle system and test method thereof 失效
标题翻译：快速随机循环系统的同步半导体存储器件及其测试方法
公开(公告)号：US06973000B2
公开(公告)日：2005-12-06
申请号：US10662780
申请日：2003-09-15
申请人： Kazuko Inuzuka , Kazuaki Kawaguchi
发明人： Kazuko Inuzuka , Kazuaki Kawaguchi
IPC分类号： G01R31/30 , G01R31/28 , G01R31/3185 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C29/14 , G11C29/46 , G11C7/00
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C11/401 , G11C11/4076 , G11C29/12015 , G11C29/14 , G11C29/46 , G11C29/48
摘要： An FCRAM includes first to third circuits. The first circuit generates a first signal based on a command detection signal. The second circuit is configured to receive the command detection signal, an operation mode specifying signal and a selection signal and generate a second signal which causes the start timing of the operation of a row-system circuit to be synchronized with the input timing of a second command. The third circuit is configured to select the first signal when a normal operation mode is specified by the operation mode specifying signal, select the second signal when a test mode is specified, and generate a third signal used to activate at least part of the memory cells in a memory cell array based on a selected one of the first and second signals and the selection signal.
摘要翻译： FCRAM包括第一至第三电路。第一电路基于命令检测信号产生第一信号。第二电路被配置为接收命令检测信号，操作模式指定信号和选择信号，并且生成使行系统电路的操作的开始定时与第二信号的输入定时同步的第二信号命令。第三电路被配置为当通过操作模式指定信号指定正常操作模式时选择第一信号，当指定测试模式时选择第二信号，并且生成用于激活至少部分存储器单元的第三信号在基于第一和第二信号中选择的一个和选择信号的存储单元阵列中。

7. 发明申请

US20060034145A1 Synchronous semiconductor memory device of fast random cycle system and test method thereof 失效
公开(公告)号：US20060034145A1
公开(公告)日：2006-02-16
申请号：US11244606
申请日：2005-10-05
申请人： Kazuko Inuzuka , Kazuaki Kawaguchi
发明人： Kazuko Inuzuka , Kazuaki Kawaguchi
IPC分类号： G11C8/00
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C11/401 , G11C11/4076 , G11C29/12015 , G11C29/14 , G11C29/46 , G11C29/48
摘要： An FCRAM includes first to third circuits. The first circuit generates a first signal based on a command detection signal. The second circuit is configured to receive the command detection signal, an operation mode specifying signal and a selection signal and generate a second signal which causes the start timing of the operation of a row-system circuit to be synchronized with the input timing of a second command. The third circuit is configured to select the first signal when a normal operation mode is specified by the operation mode specifying signal, select the second signal when a test mode is specified, and generate a third signal used to activate at least part of the memory cells in a memory cell array based on a selected one of the first and second signals and the selection signal.

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