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1. 发明授权

US5904609A Polishing apparatus and polishing method 失效
标题翻译：抛光设备和抛光方法
公开(公告)号：US5904609A
公开(公告)日：1999-05-18
申请号：US637433
申请日：1996-04-25
申请人： Atsushi Fukuroda , Yoshihiro Arimoto , Ko Nakamura
发明人： Atsushi Fukuroda , Yoshihiro Arimoto , Ko Nakamura
IPC分类号： B24B37/04 , G05B19/416 , B24B49/00
CPC分类号： B24B37/005 , G05B19/4163 , G05B2219/45199 , G05B2219/45232 , G05B2219/49085
摘要： A polishing apparatus comprises a first surface plate for supporting a polishing object, a driving mechanism for rotating the first surface plate, a second surface plate arranged so as to oppose to the first surface plate, an abrasive cloth stuck to the second surface plate, a vibration detector attached to the first surface plate or the second surface plate for detecting vibration in polishing, a controlling portion for controlling polishing operation of the first surface plate and the second surface plate, and signal analyzing unit for analyzing vibration intensity detected by the a vibration detector through frequency analysis, integrating the vibration intensity relative to time, and transmitting a polishing stop signal to stop polishing operation of the first surface plate and the second surface plate to the controlling portion when variation in a resultant integral value relative to time is less than a first reference value or when the resultant integral value is less than a second reference value.
摘要翻译：抛光装置包括用于支撑抛光对象的第一表面板，用于旋转第一表面板的驱动机构，与第一表面板相对布置的第二表面板，粘附到第二表面板的研磨布，振动检测器，附接到第一表面板或第二表面板，用于检测抛光中的振动;控制部分，用于控制第一表面板和第二表面板的抛光操作;以及信号分析单元，用于分析由振动检测的振动强度检测器通过频率分析，相对于时间的振动强度积分，并且当所得到的积分值相对于时间的变化小于时，传递抛光停止信号以停止将第一表面板和第二表面板的抛光操作到控制部分第一参考值或当所得积分值小于seco时 nd参考值。

2. 发明授权

US5399233A Method of and apparatus for manufacturing a semiconductor substrate 失效
标题翻译：用于制造半导体衬底的方法和装置
公开(公告)号：US5399233A
公开(公告)日：1995-03-21
申请号：US969290
申请日：1993-02-01
申请人： Maki Murazumi , Yoshihiro Arimoto , Atsushi Fukuroda
发明人： Maki Murazumi , Yoshihiro Arimoto , Atsushi Fukuroda
IPC分类号： H01L21/304 , H01L21/306 , H01L21/762 , H01L27/12
CPC分类号： H01L21/30625 , H01L21/76251 , Y10S438/959 , Y10S438/977
摘要： In a process of manufacturing a semiconductor substrate having a SOI (silicon on insulator) structure, grooves are formed in a silicon layer reduced in thickness to several microns so that the silicon layer is separated into island-like regions corresponding to a chip size or device regions, and a stopper having a thickness corresponding to a desired final thickness of the silicon layer is formed in the grooves. The silicon layer is scanned with a piece of polishing cloth which has an area larger than that of each island-like region but sufficiently smaller than that of silicon layer and which is attached to a pressing surface of the polishing jig, thereby polishing the silicon layer until the stopper is exposed. The thickness of the silicon layer is measured at a position such that the thickness of a portion thereof is measured immediately before the same portion is polished. The pressure applied to the polishing cloth or the rotational speed of the polishing jig is controlled on the basis of thickness data thereby obtained. The thickness of a silicon layer having a diameter of 6 inches was thereby reduced uniformly to 0.1 to 1 .mu.m.
摘要翻译： PCT No.PCT / JP92 / 01586 Sec。 371日期：1993年2月1日在制造具有SOI（绝缘体上硅）结构的半导体衬底的工艺中，在厚度减小到几微米的硅层中形成凹槽，因此，硅层被分离成对应于芯片尺寸或器件区域的岛状区域，并且在沟槽中形成具有对应于硅层的期望最终厚度的厚度的塞子。用一块抛光布扫描硅层，该抛光布的面积大于每个岛状区域的面积，但比硅层的面积大得多，并附着在抛光夹具的压制表面上，从而抛光硅层直到塞子被暴露。测量硅层的厚度，使其一部分的厚度在相同部分被抛光之前立即测量。基于由此获得的厚度数据来控制施加到抛光布上的压力或抛光夹具的转速。因此，直径为6英寸的硅层的厚度均匀地降低至0.1至1μm。

3. 发明授权

US5621239A SOI device having a buried layer of reduced resistivity 失效
标题翻译：具有降低电阻率的掩埋层的SOI器件
公开(公告)号：US5621239A
公开(公告)日：1997-04-15
申请号：US475439
申请日：1995-06-07
申请人： Hiroshi Horie , Atsushi Fukuroda , Yoshihiro Arimoto
发明人： Hiroshi Horie , Atsushi Fukuroda , Yoshihiro Arimoto
IPC分类号： H01L21/762 , H01L21/86 , H01L29/73 , H01L29/00 , H01L27/01
CPC分类号： H01L29/7317 , H01L21/76251 , H01L21/86
摘要： In a semiconductor device, first and second substrates are supported with respective first major surfaces in opposing, parallel and spaced relationship. A conductor layer of low resistivity material is provided on a selected one of the opposing and spaced major surfaces, in intimate contact and spaced from the opposed major surface of the other substrate. An active device is formed in the first substrate with a region electrically connected to the conductor layer. A contact region is exposed at the second major surface of the first substrate and extends through the first substrate and into electrical contact with the conductor layer.
摘要翻译：在半导体器件中，第一和第二衬底以相对的，平行和间隔的关系以相应的第一主表面支撑。低电阻率材料的导体层设置在所选择的一个相对的和间隔开的主表面上，与另一个基板的相对的主表面紧密接触并间隔开。有源器件在第一衬底中形成有电连接到导体层的区域。接触区域暴露在第一基板的第二主表面处并延伸穿过第一基板并与导体层电接触。

4. 发明授权

US6114247A Polishing cloth for use in a CMP process and a surface treatment thereof 失效
标题翻译：用于CMP工艺的抛光布及其表面处理
公开(公告)号：US6114247A
公开(公告)日：2000-09-05
申请号：US884549
申请日：1997-06-27
申请人： Ko Nakamura , Sadahiro Kishii , Yoshihiro Arimoto
发明人： Ko Nakamura , Sadahiro Kishii , Yoshihiro Arimoto
IPC分类号： B24B53/017 , B24D11/00 , B24D13/12 , C09G1/02 , H01L21/02 , H01L21/304 , H01L21/3105 , H01L21/321 , H01L21/302
CPC分类号： B24B53/013 , B24B37/044 , B24B53/017 , C09G1/02 , H01L21/02065 , H01L21/02074 , H01L21/31053 , H01L21/3212
摘要： A method of fabricating a semiconductor device includes a step of polishing a surface of a substrate by a chemical mechanical polishing process conducted on a polishing cloth by a slurry. The polishing is conducted so that projections having a height of about 30 .mu.m or less are formed on the polishing cloth with an interval of about 55 .mu.m or less as a result of the polishing.
摘要翻译：制造半导体器件的方法包括通过在抛光布上通过浆料进行的化学机械抛光工艺来抛光衬底的表面的步骤。进行研磨，由此抛光的结果，在研磨布上以约55μm以下的间隔形成高度约30μm以下的凸起。

5. 发明授权

US6159858A Slurry containing manganese oxide and a fabrication process of a semiconductor device using such a slurry 失效
标题翻译：含有锰氧化物的浆料和使用这种浆料的半导体器件的制造方法
公开(公告)号：US6159858A
公开(公告)日：2000-12-12
申请号：US884165
申请日：1997-06-27
申请人： Sadahiro Kishii , Ko Nakamura , Yoshihiro Arimoto , Akiyoshi Hatada , Rintaro Suzuki , Naruo Ueda , Kenzo Hanawa
发明人： Sadahiro Kishii , Ko Nakamura , Yoshihiro Arimoto , Akiyoshi Hatada , Rintaro Suzuki , Naruo Ueda , Kenzo Hanawa
IPC分类号： C03C19/00 , C09G1/02 , C09K3/14 , C09K13/04 , H01L21/02 , H01L21/306 , H01L21/3105 , H01L21/321 , H01L21/302
CPC分类号： C09G1/02 , C03C19/00 , C09K3/1409 , C09K3/1463 , C09K3/1472 , C09K13/04 , H01L21/02065 , H01L21/02074 , H01L21/31053 , H01L21/3212
摘要： A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.
摘要翻译：浆料含有MnO 2或其它氧化锰作为磨料颗粒的主要成分。此外，公开了使用这种氧化锰研磨剂的研磨工艺和使用这种抛光工艺的半导体器件的制造工艺。

6. 发明授权

US5877089A Slurry containing manganese oxide 失效
标题翻译：含有氧化锰的浆料
公开(公告)号：US5877089A
公开(公告)日：1999-03-02
申请号：US14246
申请日：1998-01-27
申请人： Sadahiro Kishii , Akiyoshi Hatada , Rintaro Suzuki , Hiroshi Horie , Yoshihiro Arimoto , Ko Nakamura
发明人： Sadahiro Kishii , Akiyoshi Hatada , Rintaro Suzuki , Hiroshi Horie , Yoshihiro Arimoto , Ko Nakamura
IPC分类号： C09G1/02 , C09K3/14 , H01L21/3105 , H01L21/463
CPC分类号： H01L21/31053 , C09G1/02 , C09K3/1463 , H01L21/463
摘要： A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.
摘要翻译：浆料含有MnO 2或其它氧化锰作为磨料颗粒的主要成分。此外，公开了使用这种氧化锰研磨剂的研磨工艺和使用这种抛光工艺的半导体器件的制造工艺。

7. 发明授权

US5763325A Fabrication process of a semiconductor device using a slurry containing manganese oxide 失效
标题翻译：使用含有氧化锰的浆料的半导体器件的制造方法
公开(公告)号：US5763325A
公开(公告)日：1998-06-09
申请号：US674507
申请日：1996-07-02
申请人： Sadahiro Kishii , Akiyoshi Hatada , Rintaro Suzuki , Hiroshi Horie , Yoshihiro Arimoto , Ko Nakamura
发明人： Sadahiro Kishii , Akiyoshi Hatada , Rintaro Suzuki , Hiroshi Horie , Yoshihiro Arimoto , Ko Nakamura
IPC分类号： C09G1/02 , C09K3/14 , H01L21/3105 , H01L21/463
CPC分类号： H01L21/31053 , C09G1/02 , C09K3/1463 , H01L21/463
摘要： A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.
摘要翻译：浆料含有MnO 2或其它氧化锰作为磨料颗粒的主要成分。此外，公开了使用这种氧化锰研磨剂的研磨工艺和使用这种抛光工艺的半导体器件的制造工艺。

8. 发明授权

US5413951A Composite semiconductor substrate and a fabrication process thereof 失效
标题翻译：复合半导体衬底及其制造工艺
公开(公告)号：US5413951A
公开(公告)日：1995-05-09
申请号：US19888
申请日：1993-02-19
申请人： Tatsuya Ohori , Isamu Hanyu , Fumitoshi Sugimoto , Yoshihiro Arimoto
发明人： Tatsuya Ohori , Isamu Hanyu , Fumitoshi Sugimoto , Yoshihiro Arimoto
IPC分类号： H01L27/12 , H01L21/02 , H01L21/20 , H01L27/01 , H01L29/04 , H01L21/302
CPC分类号： H01L21/76256 , H01L21/2007 , Y10S148/135
摘要： A method for fabricating an SOI structure which includes the steps of contacting a single crystal layer of a group III-V compound semiconductor material to a single crystal substrate of sapphire such that a principal surface of said single crystal layer establishes an intimate contact with a corresponding principal surface of said single crystal substrate and bonding the single crystal layer and the single crystal substrate with each other while elevating a temperature.
摘要翻译：一种制造SOI结构的方法，其包括将III-V族化合物半导体材料的单晶层与蓝宝石的单晶衬底接触的步骤，使得所述单晶层的主表面与相应的所述单晶基板的主表面，并且在升高温度的同时将单晶层和单晶基板彼此接合。

9. 发明授权

US5506433A Composite semiconductor substrate having a single crystal substrate and a single crystal layer formed thereon 失效
标题翻译：具有单晶基板和形成在其上的单晶层的复合半导体基板
公开(公告)号：US5506433A
公开(公告)日：1996-04-09
申请号：US277022
申请日：1994-08-24
申请人： Tatsuya Ohori , Isamu Hanyu , Fumitoshi Sugimoto , Yoshihiro Arimoto
发明人： Tatsuya Ohori , Isamu Hanyu , Fumitoshi Sugimoto , Yoshihiro Arimoto
IPC分类号： H01L27/12 , H01L21/02 , H01L21/20 , H01L27/01 , H01L29/04
CPC分类号： H01L21/76256 , H01L21/2007 , Y10S148/135
摘要： A silicon-on-insulator (SOI) structure having a single crystal layer of a group III-V compound semiconductor material contacting a single crystal substrate of sapphire such that a principal surface of the single crystal layer establishes an intimate contact with a corresponding principal surface of the single crystal substrate and the single crystal layer, and the single crystal substrate are bonded with each other while elevating a temperature.
摘要翻译：一种绝缘体上硅（SOI）结构，其具有接触蓝宝石单晶衬底的III-V族化合物半导体材料的单晶层，使得单晶层的主表面与相应的主表面紧密接触的单晶衬底和单晶层，并且单晶衬底在升高温度的同时彼此接合。

10. 发明授权

US5037774A Process for the production of semiconductor devices utilizing multi-step deposition and recrystallization of amorphous silicon 失效
标题翻译：利用多步沉积和非晶硅再结晶生产半导体器件的方法
公开(公告)号：US5037774A
公开(公告)日：1991-08-06
申请号：US73839
申请日：1987-07-15
申请人： Hideki Yamawaki , Yoshihiro Arimoto , Shigeo Kodama , Takafumi Kimura , Masaru Ihara
发明人： Hideki Yamawaki , Yoshihiro Arimoto , Shigeo Kodama , Takafumi Kimura , Masaru Ihara
IPC分类号： H01L27/12 , H01L21/20 , H01L21/205 , H01L21/324 , H01L21/86
CPC分类号： H01L21/324 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02532 , H01L21/0262 , Y10S148/017 , Y10S148/025 , Y10S148/15
摘要： Process for the production of semiconductor devices by using silicon-on-insulator (SOI) techniques. The Si layers of the SOI structure include an interfacial layer of Si and a buffer layer of Si formed thereon, whereby the formation of stacking faults in the Si layers can be effectively prevented. Pretreatment of the underlying insulating material with a molybdate solution and interposition of an additional layer of slowly grown single-crystalline Si between the buffer layer of Si and the overlying active Si layer are also effective to inhibit the stacking faults. Semiconductor devices with high quality can be produced with good yield.
摘要翻译：通过使用绝缘体上硅（SOI）技术制造半导体器件的工艺。 SOI结构的Si层包括Si的界面层和在其上形成的Si的缓冲层，由此可以有效地防止在Si层中形成堆垛层错。用钼酸盐溶液预处理下层绝缘材料，并在Si的缓冲层和上覆的有源Si层之间插入缓慢生长的单晶Si的附加层也有效地抑制堆垛层错。可以以良好的产量生产具有高质量的半导体器件。

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