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1. 发明授权

US5399233A Method of and apparatus for manufacturing a semiconductor substrate 失效
标题翻译：用于制造半导体衬底的方法和装置
公开(公告)号：US5399233A
公开(公告)日：1995-03-21
申请号：US969290
申请日：1993-02-01
申请人： Maki Murazumi , Yoshihiro Arimoto , Atsushi Fukuroda
发明人： Maki Murazumi , Yoshihiro Arimoto , Atsushi Fukuroda
IPC分类号： H01L21/304 , H01L21/306 , H01L21/762 , H01L27/12
CPC分类号： H01L21/30625 , H01L21/76251 , Y10S438/959 , Y10S438/977
摘要： In a process of manufacturing a semiconductor substrate having a SOI (silicon on insulator) structure, grooves are formed in a silicon layer reduced in thickness to several microns so that the silicon layer is separated into island-like regions corresponding to a chip size or device regions, and a stopper having a thickness corresponding to a desired final thickness of the silicon layer is formed in the grooves. The silicon layer is scanned with a piece of polishing cloth which has an area larger than that of each island-like region but sufficiently smaller than that of silicon layer and which is attached to a pressing surface of the polishing jig, thereby polishing the silicon layer until the stopper is exposed. The thickness of the silicon layer is measured at a position such that the thickness of a portion thereof is measured immediately before the same portion is polished. The pressure applied to the polishing cloth or the rotational speed of the polishing jig is controlled on the basis of thickness data thereby obtained. The thickness of a silicon layer having a diameter of 6 inches was thereby reduced uniformly to 0.1 to 1 .mu.m.
摘要翻译： PCT No.PCT / JP92 / 01586 Sec。 371日期：1993年2月1日在制造具有SOI（绝缘体上硅）结构的半导体衬底的工艺中，在厚度减小到几微米的硅层中形成凹槽，因此，硅层被分离成对应于芯片尺寸或器件区域的岛状区域，并且在沟槽中形成具有对应于硅层的期望最终厚度的厚度的塞子。用一块抛光布扫描硅层，该抛光布的面积大于每个岛状区域的面积，但比硅层的面积大得多，并附着在抛光夹具的压制表面上，从而抛光硅层直到塞子被暴露。测量硅层的厚度，使其一部分的厚度在相同部分被抛光之前立即测量。基于由此获得的厚度数据来控制施加到抛光布上的压力或抛光夹具的转速。因此，直径为6英寸的硅层的厚度均匀地降低至0.1至1μm。

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