专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050058005A1 Method for operating a memory device 有权
标题翻译：操作存储器件的方法
公开(公告)号：US20050058005A1
公开(公告)日：2005-03-17
申请号：US10747217
申请日：2003-12-30
申请人： Assaf Shappir , Dror Avni , Boaz Eitan
发明人： Assaf Shappir , Dror Avni , Boaz Eitan
IPC分类号： G11C16/02 , G11C16/04 , G11C16/34 , G11C29/02 , G11C29/50 , G11C8/02
CPC分类号： G11C29/50 , G11C16/04 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50004
摘要： A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.
摘要翻译：一种用于操作存储器阵列中的存储器单元的位的方法和系统，所述方法包括将第一操作脉冲施加到第一单元的端子，所述第一操作脉冲旨在将所述第一单元放置在预定状态; 以及将第二操作脉冲施加到所述组中的第二小区的终端，所述第二操作脉冲旨在将所述第二小区置于所述预定状态，并且所述第二操作脉冲的脉冲特性是所述第二操作脉冲的响应的函数第一个电池到第一个工作脉冲。

2. 发明授权

US07079420B2 Method for operating a memory device 有权
标题翻译：操作存储器件的方法
公开(公告)号：US07079420B2
公开(公告)日：2006-07-18
申请号：US10747217
申请日：2003-12-30
申请人： Assaf Shappir , Dror Avni , Boaz Eitan
发明人： Assaf Shappir , Dror Avni , Boaz Eitan
IPC分类号： G11C16/04
CPC分类号： G11C29/50 , G11C16/04 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50004
摘要： A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.
摘要翻译：一种用于操作存储器阵列中的存储器单元的位的方法和系统，所述方法包括将第一操作脉冲施加到第一单元的端子，所述第一操作脉冲旨在将所述第一单元放置在预定状态; 以及将第二操作脉冲施加到所述组中的第二小区的终端，所述第二操作脉冲旨在将所述第二小区置于所述预定状态，并且所述第二操作脉冲的脉冲特性是所述第二操作脉冲的响应的函数第一个电池到第一个工作脉冲。

3. 发明授权

US07420848B2 Method, system, and circuit for operating a non-volatile memory array 有权
标题翻译：用于操作非易失性存储器阵列的方法，系统和电路
公开(公告)号：US07420848B2
公开(公告)日：2008-09-02
申请号：US11328015
申请日：2006-01-09
申请人： Assaf Shappir , Dror Avni , Boaz Eitan
发明人： Assaf Shappir , Dror Avni , Boaz Eitan
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C29/50 , G11C16/04 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50004
摘要： A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.
摘要翻译：一种用于操作存储器阵列中的存储器单元的位的方法和系统，所述方法包括将第一操作脉冲施加到第一单元的端子，所述第一操作脉冲旨在将所述第一单元放置在预定状态; 以及将第二操作脉冲施加到所述组中的第二小区的终端，所述第二操作脉冲旨在将所述第二小区置于所述预定状态，并且所述第二操作脉冲的脉冲特性是所述第二操作脉冲的响应的函数第一个电池到第一个工作脉冲。

4. 发明申请

US20060126396A1 Method, system, and circuit for operating a non-volatile memory array 有权
标题翻译：用于操作非易失性存储器阵列的方法，系统和电路
公开(公告)号：US20060126396A1
公开(公告)日：2006-06-15
申请号：US11328015
申请日：2006-01-09
申请人： Assaf Shappir , Dror Avni , Boaz Eitan
发明人： Assaf Shappir , Dror Avni , Boaz Eitan
IPC分类号： G11C16/04
CPC分类号： G11C29/50 , G11C16/04 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50004
摘要： A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.
摘要翻译：一种用于操作存储器阵列中的存储器单元的位的方法和系统，所述方法包括将第一操作脉冲施加到第一单元的端子，所述第一操作脉冲旨在将所述第一单元放置在预定状态; 以及将第二操作脉冲施加到所述组中的第二小区的终端，所述第二操作脉冲旨在将所述第二小区置于所述预定状态，并且所述第二操作脉冲的脉冲特性是所述第二操作脉冲的响应的函数第一个电池到第一个工作脉冲。

5. 发明授权

US06700818B2 Method for operating a memory device 有权
标题翻译：操作存储器件的方法
公开(公告)号：US06700818B2
公开(公告)日：2004-03-02
申请号：US10211248
申请日：2002-08-05
申请人： Assaf Shappir , Dror Avni , Boaz Eitan
发明人： Assaf Shappir , Dror Avni , Boaz Eitan
IPC分类号： G11C1604
CPC分类号： G11C29/50 , G11C16/04 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50004
摘要： A method for operating bits of memory cells in a memory array, the method including applying operating pulses to bits of a sample of memory cells, determining a response of at least one of an electrical, physical and mechanical property (e.g., threshold voltage) of the bits to the operating pulses, and applying at least one further operating pulse to the rest of the array, the at least one further operating pulse being a function of the response.
摘要翻译：一种用于操作存储器阵列中的存储器单元的位的方法，所述方法包括将操作脉冲施加到存储器单元的样本的位，确定电，物理和机械属性（例如，阈值电压）中的至少一个的响应所述比特到所述操作脉冲，以及向所述阵列的其余部分施加至少一个另外的操作脉冲，所述至少一个另外的操作脉冲是所述响应的函数。

6. 发明授权

US07638850B2 Non-volatile memory structure and method of fabrication 有权
标题翻译：非易失性存储器结构和制造方法
公开(公告)号：US07638850B2
公开(公告)日：2009-12-29
申请号：US11440624
申请日：2006-05-24
申请人： Eli Lusky , Assaf Shappir , Rustom Irani , Boaz Eitan
发明人： Eli Lusky , Assaf Shappir , Rustom Irani , Boaz Eitan
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L21/28282 , H01L21/32139 , H01L27/11568 , H01L29/66833
摘要： A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.
摘要翻译：一种用于创建非易失性存储器阵列的方法包括至少在给定宽度的掩模列之间以及至少穿过覆盖衬底的ONO层之间的衬底中注入口袋植入物，从掩模柱产生增加宽度的多晶硅柱，产生位至少在增宽宽度的多晶硅柱之间并且至少在多晶硅柱之间沉积氧化物的衬底中的线。

7. 发明申请

US20080025084A1 High aspect ration bitline oxides 审中-公开
标题翻译：高比例位线氧化物
公开(公告)号：US20080025084A1
公开(公告)日：2008-01-31
申请号：US11882787
申请日：2007-08-06
申请人： Rustom Irani , Boaz Eitan , Assaf Shappir
发明人： Rustom Irani , Boaz Eitan , Assaf Shappir
IPC分类号： G11C11/34 , H01L21/336 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11568
摘要： A non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area, an oxide-nitride-oxide (ONO) layer within the word line areas and at least partially within the contact areas and protective elements, generated when spacers are formed in the periphery area, to protect silicon under the ONO layer in the contact areas. A non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area and bitline oxides whose height:distance aspect ratio (T:D) is at least 25% greater than the maximum height:distance (Tg:Dg) ratio of gate electrodes in the CMOS periphery to ensure remnants of sidewall material between bitlines after sidewall spacer etch, thus protecting silicon in a subsequent word line salicidation step.
摘要翻译：非易失性存储器件包括多个字线区域，每个字线区域与其相邻部分由接触区域分开，字线区域内的氧化物 - 氧化物 - 氧化物（ONO）层和至少部分地在接触区域内的保护元件，当在周边区域中形成间隔物时产生，以保护接触区域内的ONO层下的硅。非易失性存储器件包括多个字线区域，每个字线区域与其相邻的接触区域分开，并且其高度：距离长宽比（T：D）比最大高度大至少25％的位线氧化物：距离（Tg ：Dg）CMOS外围的栅电极的比例，以确保在侧壁间隔物蚀刻之后位线之间的侧壁材料的残留物，从而在随后的字线盐化步骤中保护硅。

8. 发明申请

US20060211188A1 Non-volatile memory structure and method of fabrication 有权
公开(公告)号：US20060211188A1
公开(公告)日：2006-09-21
申请号：US11440624
申请日：2006-05-24
申请人： Eli Lusky , Assaf Shappir , Rustom Irani , Boaz Eitan
发明人： Eli Lusky , Assaf Shappir , Rustom Irani , Boaz Eitan
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/31
CPC分类号： H01L27/115 , H01L21/28282 , H01L21/32139 , H01L27/11568 , H01L29/66833
摘要： A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.

9. 发明申请

US20100173464A1 Non-volatile memory structure and method of fabrication 有权
标题翻译：非易失性存储器结构和制造方法
公开(公告)号：US20100173464A1
公开(公告)日：2010-07-08
申请号：US12654092
申请日：2009-12-10
申请人： Eli Lusky , Assaf Shappir , Rustom Irani , Boaz Eitan
发明人： Eli Lusky , Assaf Shappir , Rustom Irani , Boaz Eitan
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/28282 , H01L21/32139 , H01L27/11568 , H01L29/66833
摘要： A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.
摘要翻译：一种用于创建非易失性存储器阵列的方法包括至少在给定宽度的掩模列之间以及至少穿过覆盖衬底的ONO层之间的衬底中注入口袋植入物，从掩模柱产生增加宽度的多晶硅柱，产生位至少在增宽宽度的多晶硅柱之间并且至少在多晶硅柱之间沉积氧化物的衬底中的线。

10. 发明申请

US20090201741A1 Non-volatile memory cell with injector 有权
标题翻译：带注射器的非易失性存储单元
公开(公告)号：US20090201741A1
公开(公告)日：2009-08-13
申请号：US12318789
申请日：2009-01-08
申请人： Boaz Eitan , Maria Kushnir , Assaf Shappir
发明人： Boaz Eitan , Maria Kushnir , Assaf Shappir
IPC分类号： G11C16/06 , H01L29/792
CPC分类号： H01L29/792 , G11C16/0475 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/518
摘要： In a nonvolatile memory (NVM) cell, an injector having one or more layers of material with a lower potential barrier for holes is disposed between a charge storage stack and a source of holes (the gate for top injection, the substrate for bottom injection), to facilitate hole tunneling from the source of holes into the charge-storage layer of the charge storage stack. The injector has a barrier potential for holes which is less than an insulating layer of the charge-storage stack which is oriented towards the source of holes. A multi-layer crested barrier injector may have layers of increasing potential barriers for holes from the source to the charge-storage layer. Methods of operating NVM cells are disclosed. The NVM cell may be NROM, SONOS, or other oxide-nitride technology NVM cells such as SANOS, MANOS, TANOS.
摘要翻译：在非易失性存储器（NVM）单元中，具有一个或多个具有较低的空穴势垒的材料层的注入器设置在电荷存储堆叠和空穴源之间（用于顶部注入的栅极，用于底部注入的衬底）以便于从孔源穿孔到电荷存储堆的电荷存储层中。喷射器具有小于电荷存储堆的绝缘层的孔的势垒势垒，该绝缘层朝向孔源。多层波峰势垒注入器可以具有从源到电荷存储层的空穴的增加的势垒层。公开了操作NVM单元的方法。 NVM单元可以是NROM，SONOS或其它氧化物氮化物技术NVM单元，例如SANOS，MANOS，TANOS。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式