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1. 发明授权

US07477636B2 Processor with scheduler architecture supporting multiple distinct scheduling algorithms 有权
标题翻译：具有调度器架构的处理器，支持多种不同的调度算法
公开(公告)号：US07477636B2
公开(公告)日：2009-01-13
申请号：US10722933
申请日：2003-11-26
申请人： Asif Q. Khan , David B. Kramer , David P. Sonnier
发明人： Asif Q. Khan , David B. Kramer , David P. Sonnier
IPC分类号： H04B7/212
CPC分类号： H04L47/2441 , H04L47/22 , H04L47/50 , H04L47/522 , H04L47/568 , H04L47/58 , H04L2012/5679
摘要： A processor includes a scheduler operative to schedule data blocks for transmission from a plurality of queues or other transmission elements, utilizing at least a first table and a second table. The first table may comprise at least first and second first-in first-out (FIFO) lists of entries corresponding to transmission elements for which data blocks are to be scheduled in accordance with a first scheduling algorithm, such as a weighted fair queuing scheduling algorithm. The scheduler maintains a first table pointer identifying at least one of the first and second lists of the first table as having priority over the other of the first and second lists of the first table. The second table includes a plurality of entries corresponding to transmission elements for which data blocks are to be scheduled in accordance with a second scheduling algorithm, such as a constant bit rate or variable bit rate scheduling algorithm.
摘要翻译：处理器包括调度器，其利用至少第一表和第二表来调度用于从多个队列或其他传输元件传输的数据块。第一表可以包括对应于根据第一调度算法（例如加权公平排队调度算法）对数据块进行调度的传输元件的条目的至少第一和第二先进先出（FIFO）列表。调度器维护第一表指针，其将第一表的第一列表和第二列表中的至少一个列表标识为优先于第一表的第一和第二列表中的另一列。第二表包括对应于根据诸如恒定比特率或可变比特率调度算法的第二调度算法对其数据块进行调度的传输元件的多个条目。

2. 发明授权

US07411972B2 Link layer device with non-linear polling of multiple physical layer device ports 有权
标题翻译：具有多个物理层设备端口的非线性轮询的链路层设备
公开(公告)号：US07411972B2
公开(公告)日：2008-08-12
申请号：US10768764
申请日：2004-01-30
申请人： Asif Q. Khan , David B. Kramer
发明人： Asif Q. Khan , David B. Kramer
IPC分类号： H04L12/403 , H04L12/56 , H04J14/00
CPC分类号： H04L41/00
摘要： In a communication system comprising a link layer device connectable to one or more physical layer devices, at least a given one of a plurality of ports of the one or more physical layer devices is designated as a port for which status information is to be requested by the link layer device on a more frequent basis than such information is to be requested for one or more other ports of the plurality of ports. The ports are then polled by the link layer device in accordance with a non-linear polling sequence such that the at least one designated port is polled more frequently than the one or more other ports. The designated port may comprise a port to which the link layer device transmits data in conjunction with a current data transfer. The non-linear polling sequence may thus be altered dynamically based on particular data transfers that are occurring between a link layer device and a physical layer device in a communication system.
摘要翻译：在包括可连接到一个或多个物理层设备的链路层设备的通信系统中，一个或多个物理层设备的多个端口中的至少一个给定的一个被指定为要由其请求状态信息的端口对于多个端口中的一个或多个其他端口，要求比这种信息更频繁的链路层设备。然后根据非线性轮询序列由链路层设备轮询端口，使得至少一个指定端口比一个或多个其他端口更频繁地轮询。指定端口可以包括链路层设备结合当前数据传输发送数据的端口。因此，可以基于在通信系统中的链路层设备和物理层设备之间发生的特定数据传输来动态地改变非线性轮询序列。

3. 发明授权

US07159061B2 Link layer device with configurable address pin allocation 有权
标题翻译：链路层设备具有可配置的地址引脚分配
公开(公告)号：US07159061B2
公开(公告)日：2007-01-02
申请号：US10744567
申请日：2003-12-23
申请人： Asif Q. Khan , David B. Kramer
发明人： Asif Q. Khan , David B. Kramer
IPC分类号： H03M7/20 , G06F12/00 , G06F13/14 , G06F13/00 , G06F11/00
CPC分类号： G06F13/385
摘要： Techniques are disclosed for flexible allocation of address pins of an interface bus to particular sub-buses of the interface bus. The interface bus is between at least one physical layer device and a link layer device in a communication system. Each of the sub-buses has an interface block of the link layer device associated therewith, the interface bus being configurable to carry a composite address signal having a plurality of portions each associated with one of the address pins of the interface bus. The interface blocks of the link layer device are controlled such that each of at least a subset of the interface blocks utilizes only particular ones of the address pins that are controllably allocated to the associated sub-bus in accordance with configuration information stored in the link layer device. The composite address signal is generated as a combination of address outputs of the interface blocks.
摘要翻译：公开了用于将接口总线的地址引脚灵活分配给接口总线的特定子总线的技术。接口总线在通信系统中的至少一个物理层设备和链路层设备之间。每个子总线具有与其相关联的链路层设备的接口块，该接口总线可配置为承载具有多个部分的复合地址信号，每个部分与接口总线的一个地址引脚相关联。控制链路层设备的接口块，使得接口块的至少一个子集中的每一个仅使用根据存储在链路层中的配置信息可控地分配给相关联的子总线的特定地址引脚设备。复合地址信号作为接口块的地址输出的组合生成。

4. 发明授权

US06625683B1 Automatic early PCI transaction retry 有权
标题翻译：自动早期PCI事务重试
公开(公告)号：US06625683B1
公开(公告)日：2003-09-23
申请号：US09379018
申请日：1999-08-23
申请人： Asif Q. Khan , James O. Mergard
发明人： Asif Q. Khan , James O. Mergard
IPC分类号： G06F1320
CPC分类号： G06F13/4027
摘要： A bus bridge mechanism is provided with an automatic delayed transaction enable mode. When the automatic delayed transaction enable mode is activated, a bus master making a read request is immediately signaled to retry the transaction, and the read request is treated by the bus bridge as a delayed read request to be completed asynchronously. The delayed read request, when completed, supplies data to the bus master on the next retry of the read request by the bus master following the completion of the delayed read request.
摘要翻译：总线桥机构具有自动延迟事务使能模式。当自动延迟事务启用模式被激活时，立即发信号通知发送读请求的总线主机重试事务，并且读请求被总线桥处理为延迟读请求，以异步完成。延迟读取请求完成后，在完成延迟读取请求之后，总线主机在下次重试读取请求时向总线主机提供数据。

5. 发明授权

US6163826A Method and apparatus for non-concurrent arbitration of multiple busses 有权
标题翻译：多台总线不并发仲裁的方法和装置
公开(公告)号：US6163826A
公开(公告)日：2000-12-19
申请号：US378985
申请日：1999-08-23
申请人： Asif Q. Khan , James O. Mergard
发明人： Asif Q. Khan , James O. Mergard
IPC分类号： G06F13/364 , G06F13/00
CPC分类号： G06F13/364
摘要： A processor-based system such as a microcontroller supports a non-concurrent mode in which a bus master requesting ownership of a peripheral bus is forced to acquire ownership of both the peripheral bus and a processor bus. The system includes a peripheral bus arbiter to detect a peripheral bus request for the peripheral bus by a bus master, to generate a processor bus request for the processor bus in response to detecting the peripheral bus request, and to grant the bus master ownership of the peripheral bus if the bus master is granted ownership of the processor bus. The peripheral bus arbiter maintains ownership of the processor bus by the bus master until the bus master releases ownership of the peripheral bus. Similarly, a bus master seeking ownership of the processor bus can be forced to acquire ownership of the peripheral bus. The non-concurrent mode can be applied to various multi-bus architectures. One advantage of the non-concurrent mode is improved debug capability.
摘要翻译：诸如微控制器的基于处理器的系统支持非并发模式，其中要求外部总线的所有权的总线主机被迫获取外围总线和处理器总线的所有权。该系统包括外设总线仲裁器，用于通过总线主机检测外围总线的外围总线请求，以响应于检测到外围总线请求而产生处理器总线请求，并且授予总线主机所有权外设总线如果总线主机被授予处理器总线的所有权。外设总线仲裁器通过总线主机维护处理器总线的所有权，直到总线主机释放外设总线的所有权。类似地，可以迫使寻求处理器总线所有权的总线主机获得外围总线的所有权。非并发模式可以应用于各种多总线架构。非并发模式的一个优点是提高了调试能力。

6. 发明授权

US07277396B2 Processor with script-based performance monitoring 有权
标题翻译：处理器，具有基于脚本的性能监控
公开(公告)号：US07277396B2
公开(公告)日：2007-10-02
申请号：US10699037
申请日：2003-10-31
申请人： David Allen Brown , Robert A. Corley , Asif Q. Khan
发明人： David Allen Brown , Robert A. Corley , Asif Q. Khan
IPC分类号： H04L12/28 , H04L1/00
CPC分类号： H04L49/30 , H04L43/0888 , H04L49/501 , H04L49/555 , H04L69/22
摘要： A processor includes controller circuitry operative to control performance monitoring for at least one flow of cells or other protocol data units received by the processor. The controller circuitry includes a classifier and is operative to access memory circuitry associated with the processor. The classifier is configured to perform at least a first pass classification of at least a subset of the protocol data units. The controller circuitry in conjunction with a first pass classification of a protocol data unit of a first type is operative to execute a first script, and in conjunction with a first pass classification of a protocol data unit of a second type is operative to execute a second script different than the first script. A result of execution of at least one of the first and second scripts is stored in the memory circuitry. A performance monitoring output is generated, responsive to receipt of the protocol data unit of the second type, based at least in part on the result of execution of at least one of the first and second scripts. The performance monitoring output may be generated in conjunction with a second pass classification of the protocol data unit of the second type, upon execution of an additional function or other type of script.
摘要翻译：处理器包括控制器电路，其可操作以控制由处理器接收的至少一个小区或其他协议数据单元流的性能监视。控制器电路包括分类器，并且可操作以访问与处理器相关联的存储器电路。分类器被配置为执行协议数据单元的至少一个子集的至少第一遍分类。控制器电路结合第一类型的协议数据单元的第一遍分类可操作以执行第一脚本，并且结合第二类型的协议数据单元的第一遍分类可操作以执行第二类型脚本与第一个脚本不同。执行第一和第二脚本中的至少一个脚本的结果被存储在存储器电路中。至少部分地基于第一和第二脚本中的至少一个的执行结果，响应于第二类型的协议数据单元的接收而生成性能监视输出。性能监视输出可以在执行附加功能或其他类型的脚本时结合第二类型的协议数据单元的第二遍分类来生成。

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