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1. 发明授权

US08747960B2 Processes and systems for engineering a silicon-type surface for selective metal deposition to form a metal silicide 有权
标题翻译：用于工程化硅型表面以进行选择性金属沉积以形成金属硅化物的工艺和系统
公开(公告)号：US08747960B2
公开(公告)日：2014-06-10
申请号：US11513446
申请日：2006-08-30
申请人： Yezdi Dordi , John Boyd , Tiruchirapalli Arunagiri , Johan Vertommen , Fritz C. Redeker , William Thie , Arthur M. Howald
发明人： Yezdi Dordi , John Boyd , Tiruchirapalli Arunagiri , Johan Vertommen , Fritz C. Redeker , William Thie , Arthur M. Howald
IPC分类号： C23C14/02 , H05H1/00
CPC分类号： C23C18/1651 , C23C18/1893 , H01L21/0206 , H01L21/02063 , H01L21/02068 , H01L21/02074 , H01L21/28518 , H01L21/288 , H01L21/32115 , H01L21/32135 , H01L21/32136 , H01L21/67161 , H01L21/67207 , H01L21/76814 , H01L21/7684 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/76862 , Y02P70/605
摘要： The embodiments fill the need to enhance electro-migration performance, provide lower metal resistivity, and improve silicon-to-metal interfacial adhesion for copper interconnects by providing improved processes and systems that produce a silicon-to-metal interface. An exemplary method of preparing a substrate surface of a substrate to selectively deposit a layer of a metal on a silicon or polysilicon surface of the substrate to form a metal silicide in an integrated system is provided. The method includes removing organic contaminants from the substrate surface in the integrated system, and reducing the silicon or polysilicon surface in the integrated system after removing organic contaminants to convert silicon oxide on the silicon or polysilicon surface to silicon, wherein after reducing the silicon or polysilicon surface, the substrate is transferred and processed in controlled environment to prevent the formation of silicon oxide, the silicon or polysilicon surface is reduced to increase the selectivity of the metal on the silicon surface. The method further includes selectively depositing the layer of the metal on the silicon or polysilicon surface of substrate in the integrated system after reducing the silicon or polysilicon surface. An exemplary system to practice the exemplary method described above is also provided.
摘要翻译：这些实施方案通过提供产生硅 - 金属界面的改进的工艺和系统来满足增强电迁移性能，提供较低金属电阻率以及改进铜互连的硅 - 金属界面粘附的需要。提供了制备衬底的衬底表面以在衬底的硅或多晶硅表面上选择性地沉积金属层以在集成系统中形成金属硅化物的示例性方法。该方法包括从集成系统中的衬底表面去除有机污染物，以及在去除有机污染物之后减少集成系统中的硅或多晶硅表面，以将硅或多晶硅表面上的氧化硅转化为硅，其中在还原硅或多晶硅之后表面，在受控环境中转移和处理衬底以防止形成氧化硅，减少硅或多晶硅表面以增加金属在硅表面上的选择性。该方法还包括在减少硅或多晶硅表面之后，在集成系统中的衬底的硅或多晶硅表面上选择性地沉积金属层。还提供了用于实践上述示例性方法的示例性系统。

2. 发明授权

US08454794B2 Antenna for plasma processor and apparatus 失效
标题翻译：等离子体处理器和设备天线
公开(公告)号：US08454794B2
公开(公告)日：2013-06-04
申请号：US13524734
申请日：2012-06-15
申请人： Arthur M. Howald , Andras Kuthi
发明人： Arthur M. Howald , Andras Kuthi
IPC分类号： H01L21/306 , C23C16/00
CPC分类号： H01J37/321 , H01J37/32183
摘要： An antenna includes excitation terminals responsive to an RF source to supply an RF electromagnetic field to a plasma that processes a workpiece in a vacuum chamber. The coil includes a transformer having a primary winding coupled to the excitation terminals and a multi-turn plasma excitation secondary winding connected in series with a capacitor.
摘要翻译：天线包括响应于RF源的激励端子，以将RF电磁场提供给处理真空室中的工件的等离子体。线圈包括具有耦合到激励端子的初级绕组的变压器和与电容器串联连接的多匝等离子体激发次级绕组。

3. 发明授权

US08277604B2 Antenna for plasma processor and apparatus 有权
标题翻译：等离子体处理器和设备天线
公开(公告)号：US08277604B2
公开(公告)日：2012-10-02
申请号：US13020170
申请日：2011-02-03
申请人： Arthur M. Howald , Andras Kuthi
发明人： Arthur M. Howald , Andras Kuthi
IPC分类号： C23C16/00 , H01L21/306
CPC分类号： H01J37/321 , H01J37/32183
摘要： An antenna includes excitation terminals responsive to an RF source to supply an RF electromagnetic field to a plasma that processes a workpiece in a vacuum chamber. The coil includes a transformer having a primary winding coupled to the excitation terminals and a multi-turn plasma excitation secondary winding connected in series with a capacitor.
摘要翻译：天线包括响应于RF源的激励端子，以将RF电磁场提供给处理真空室中的工件的等离子体。线圈包括具有耦合到激励端子的初级绕组的变压器和与电容器串联连接的多匝等离子体激发次级绕组。

4. 发明授权

US08241701B2 Processes and systems for engineering a barrier surface for copper deposition 有权
标题翻译：用于工程用于铜沉积的阻挡面的工艺和系统
公开(公告)号：US08241701B2
公开(公告)日：2012-08-14
申请号：US11514038
申请日：2006-08-30
申请人： Yezdi Dordi , John Boyd , Tiruchirapalli Arunagiri , Hyungsuk Alexander Yoon , Fritz C. Redeker , William Thie , Arthur M. Howald
发明人： Yezdi Dordi , John Boyd , Tiruchirapalli Arunagiri , Hyungsuk Alexander Yoon , Fritz C. Redeker , William Thie , Arthur M. Howald
IPC分类号： B05D5/12
CPC分类号： H01L21/7685 , C23C18/1632 , C23C18/1651 , C23C18/1844 , H01L21/0206 , H01L21/02063 , H01L21/02068 , H01L21/02074 , H01L21/28518 , H01L21/288 , H01L21/32115 , H01L21/32135 , H01L21/32136 , H01L21/67161 , H01L21/67207 , H01L21/76814 , H01L21/7684 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/76862 , H01L21/76867 , H01L21/76871 , H01L21/76879
摘要： The embodiments fill the need to enhance electro-migration performance, provide lower metal resistivity, and improve metal-to-metal interfacial adhesion for copper interconnects by providing improved processes and systems that produce an improved metal-to-metal interface, more specifically barrier-to-copper interface. An exemplary method of preparing a substrate surface of a substrate to deposit a metallic barrier layer to line a copper interconnect structure of the substrate and to deposit a thin copper seed layer on a surface of the metallic barrier layer in an integrated system to improve electromigration performance of the copper interconnect is provided. The method includes cleaning an exposed surface of a underlying metal to remove surface metal oxide in the integrated system, wherein the underlying metal is part of a underlying interconnect electrically connected to the copper interconnect. The method also includes depositing the metallic barrier layer to line the copper interconnect structure in the integrated system, wherein after depositing the metallic barrier layer, the substrate is transferred and processed in controlled environment to prevent the formation of metallic barrier oxide. The method further includes depositing the thin copper seed layer in the integrated system, and depositing a gap-fill copper layer over the thin copper seed layer in the integrated system. An exemplary system to practice the exemplary method described above is also provided.
摘要翻译：这些实施方案通过提供改进的工艺和系统来提供改进的金属 - 金属界面，更具体地说是阻隔层，提高了电迁移性能，提供较低的金属电阻率，以及改进铜互连的金属 - 金属界面粘附的需要，到铜接口。一种制备衬底的衬底表面的示例性方法，以沉积金属阻挡层以对衬底的铜互连结构进行排列并且在集成系统中在金属阻挡层的表面上沉积薄铜籽晶层以改善电迁移性能的铜互连。该方法包括清洁底层金属的暴露表面以去除集成系统中的表面金属氧化物，其中下面的金属是与铜互连电连接的底层互连件的一部分。该方法还包括沉积金属阻挡层以在集成系统中对铜互连结构进行排列，其中在沉积金属阻挡层之后，将基底在受控环境中转移和加工以防止形成金属阻挡氧化物。该方法还包括在集成系统中沉积薄铜籽晶层，以及在集成系统中的薄铜种子层上沉积间隙填充铜层。还提供了用于实践上述示例性方法的示例性系统。

5. 发明授权

US07709400B2 Thermal methods for cleaning post-CMP wafers 有权
标题翻译：用于清洁CMP后晶圆的热处理方法
公开(公告)号：US07709400B2
公开(公告)日：2010-05-04
申请号：US11801269
申请日：2007-05-08
申请人： Zhonghui Alex Wang , Tiruchirapalli Arunagirí , Fritz C. Redeker , Yezdi Dordi , John Boyd , Mikhail Korolik , Arthur M. Howald , William Thie , Praveen Nalla
发明人： Zhonghui Alex Wang , Tiruchirapalli Arunagirí , Fritz C. Redeker , Yezdi Dordi , John Boyd , Mikhail Korolik , Arthur M. Howald , William Thie , Praveen Nalla
IPC分类号： H01L21/24 , H01L21/40 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02074
摘要： Methods for cleaning semiconductor wafers following chemical mechanical polishing are provided. An exemplary method exposes a wafer to a thermal treatment in an oxidizing environment followed by a thermal treatment in a reducing environment. The thermal treatment in the oxidizing environment both removes residues and oxidizes exposed copper surfaces to form a cupric oxide layer. The thermal treatment in the reducing environment then reduces the cupric oxide to elemental copper. This leaves the exposed copper clean and in condition for further processing, such as electroless plating.
摘要翻译：提供了化学机械抛光后的半导体晶片清洗方法。一种示例性方法将晶片暴露于氧化环境中的热处理，然后在还原环境中进行热处理。在氧化环境中的热处理既去除残留物，又氧化暴露的铜表面以形成氧化铜层。然后，在还原环境中的热处理将氧化铜还原为元素铜。这使得暴露的铜清洁并进行进一步处理，例如化学镀。

6. 发明授权

US07140374B2 System, method and apparatus for self-cleaning dry etch 有权
公开(公告)号：US07140374B2
公开(公告)日：2006-11-28
申请号：US10802460
申请日：2004-03-16
申请人： Andrew D. Bailey, III , Shrikant P. Lohokare , Arthur M. Howald , Yunsang Kim
发明人： Andrew D. Bailey, III , Shrikant P. Lohokare , Arthur M. Howald , Yunsang Kim
IPC分类号： B08B9/00 , B44C1/22
CPC分类号： B08B7/00 , B08B7/0035 , B08B7/0071 , H01J37/3244 , H01J37/32522 , H01J37/32862 , H01J2237/022 , H01L21/3065 , H01L21/32115 , H01L21/32136 , H01L21/67034 , H01L21/67051 , H01L21/67069 , H01L21/6708 , H01L21/7684 , Y10S438/905
摘要： A method for cleaning a processing chamber that includes heating an inner surface of the processing chamber to a first temperature. The first temperature can be sufficient to cause a first species to become volatile. The first species can be one of several species deposited on the inner surface. A cleaning chemistry is injected into the processing chamber. The cleaning chemistry can be reactive with a second one of the species to convert the second species to the first species. The volatilized first species can also be output from the processing chamber. A system for cleaning the process chamber is also described.

7. 发明授权

US06876155B2 Plasma processor apparatus and method, and antenna 失效
标题翻译：等离子体处理装置和方法以及天线
公开(公告)号：US06876155B2
公开(公告)日：2005-04-05
申请号：US10334063
申请日：2002-12-31
申请人： Arthur M. Howald , Andras Kuthi
发明人： Arthur M. Howald , Andras Kuthi
IPC分类号： H01J37/32 , H01J7/24
CPC分类号： H01J37/321 , H01J37/32183
摘要： An antenna includes excitation terminals responsive to an RF source to supply an RF electromagnetic field to a plasma that processes a workpiece in a vacuum chamber. A matching network includes first and second portions respectively between the source and terminals and between the terminals and the antenna plasma excitation coil. In response to indications of impedance matching between the source and its load, currents flowing between (1) the first portion and the terminals and (2) the terminals and the coil are controlled so the latter exceeds the former. The indications control impedances of the first and second portions or the first portion impedance and the source frequency. The coil can include a transformer having a primary winding coupled to the excitation terminals and a multi-turn plasma excitation secondary winding.
摘要翻译：天线包括响应于RF源的激励端子，以将RF电磁场提供给处理真空室中的工件的等离子体。匹配网络包括分别在源极和端子之间以及在端子和天线等离子体激励线圈之间的第一和第二部分。响应于源极和负载之间的阻抗匹配的指示，在（1）第一部分和端子之间流动的电流和（2）端子和线圈被控制，使得后者超过前者。第一和第二部分或第一部分阻抗和源频率的指示控制阻抗。线圈可以包括具有耦合到激励端子的初级绕组和多匝等离子体激发次级绕组的变压器。

8. 发明授权

US06646385B2 Plasma excitation coil 有权
公开(公告)号：US06646385B2
公开(公告)日：2003-11-11
申请号：US10227275
申请日：2002-08-26
申请人： Arthur M. Howald , Brian McMillin , Frank Yun Lin
发明人： Arthur M. Howald , Brian McMillin , Frank Yun Lin
IPC分类号： H01J724
CPC分类号： H01J37/321
摘要： A spiral-like multi-turn coil excites a plasma for treating a workpiece in a vacuum plasma processor. In one embodiment two of the turns have a discontinuity. Each discontinuity has a capacitor connected across it. An RF source drives the coil via a matching network, an inductor connected to one coil excitation terminal and a capacitor connected to another coil excitation terminal. The impedances of the inductors and the capacitors at the RF source frequency and the discontinuity locations are such as to cause a standing wave voltage of the coil to have (1) equal and opposite values at the coil terminals, (2) sudden amplitude and slope changes, slope reversals and polarity reversals at each of the discontinuities, and (3) three gradual standing wave voltage polarity reversals, spaced from each other by 120°. Two of the gradual polarity reversals are azimuthally aligned with the discontinuities. In a second embodiment, one turn has a discontinuity having a series capacitor connected across it. A shunt capacitor is connected between the discontinuity and ground.

9. 发明授权

US06441555B1 Plasma excitation coil 有权
标题翻译：等离子体励磁线圈
公开(公告)号：US06441555B1
公开(公告)日：2002-08-27
申请号：US09539906
申请日：2000-03-31
申请人： Arthur M. Howald , Brian McMillin , Frank Yun Lin
发明人： Arthur M. Howald , Brian McMillin , Frank Yun Lin
IPC分类号： H01J724
CPC分类号： H01J37/321
摘要： A spiral-like multi-turn coil excites a plasma for treating a workpiece in a vacuum plasma processor. In one embodiment two of the turns have a discontinuity. Each discontinuity has a capacitor connected across it. An RF source drives the coil via a matching network, an inductor connected to one coil excitation terminal and a capacitor connected to another coil excitation terminal. The impedances of the inductors and the capacitors at the RF source frequency and the discontinuity locations are such as to cause a standing wave voltage of the coil to have (1) equal and opposite values at the coil terminals, (2) sudden amplitude and slope changes, slope reversals and polarity reversals at each of the discontinuities, and (3) three gradual standing wave voltage polarity reversals, spaced from each other by 120°. Two of the gradual polarity reversals are azimuthally aligned with the discontinuities. In a second embodiment, one turn has a discontinuity having a series capacitor connected across it. A shunt capacitor is connected between the discontinuity and ground.
摘要翻译：螺旋状多匝线圈激发用于在真空等离子体处理器中处理工件的等离子体。在一个实施例中，两个匝数具有不连续性。每个不连续点都有一个连接在其上的电容器。 RF源通过匹配网络驱动线圈，连接到一个线圈激励端子的电感器和连接到另一个线圈励磁端子的电容器。在RF源频率和不连续位置处的电感器和电容器的阻抗使得线圈的驻波电压具有（1）线圈端子相等和相反的值，（2）突然的幅度和斜率每个不连续点的变化，斜率反转和极性反转，以及（3）三个逐渐驻波极性反转，彼此间隔120°。两个逐渐的极性反转与方位角对准不连续。在第二实施例中，一匝具有连接在其上的串联电容器的不连续。分流电容器连接在不连续和地之间。

10. 发明授权

US08084356B2 Methods of low-K dielectric and metal process integration 有权
标题翻译：低K电介质和金属工艺集成的方法
公开(公告)号：US08084356B2
公开(公告)日：2011-12-27
申请号：US12212611
申请日：2008-09-17
申请人： Yezdi N. Dordi , Arthur M. Howald
发明人： Yezdi N. Dordi , Arthur M. Howald
IPC分类号： H01L21/4763 , H01L21/302 , H01L21/461
CPC分类号： H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76883
摘要： An integrated process for forming metallization layers for electronic devices that use damascene structures that include low-k dielectric and metal. According to one embodiment of the present invention, the integrated process includes planarizing a gapfill metal in low-k dielectric structures, generating a protective layer on the low-k dielectric followed by cleaning the surface of the gapfill metal. Another embodiment of the present invention includes a method of protecting low-k dielectrics such as carbon doped silicon oxide.
摘要翻译：一种用于形成使用包括低k电介质和金属的镶嵌结构的电子器件的金属化层的集成方法。根据本发明的一个实施例，集成工艺包括平面化低k电介质结构中的间隙填充金属，在低k电介质上产生保护层，然后清洁间隙填充金属的表面。本发明的另一个实施方案包括保护低k电介质如碳掺杂氧化硅的方法。

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