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1. 发明授权

US07047467B1 Structure and method for verifying data in a non-JTAG device from a JTAG device with microcontroller 有权
标题翻译：用于使用微控制器从JTAG器件验证非JTAG器件中的数据的结构和方法
公开(公告)号：US07047467B1
公开(公告)日：2006-05-16
申请号：US10121064
申请日：2002-04-11
申请人： Arthur H. Khu , Farshid Shokouhi , Conrad A. Theron
发明人： Arthur H. Khu , Farshid Shokouhi , Conrad A. Theron
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/318555
摘要： According to the invention, a JTAG-compliant chip having a controller that receives data provided on the TDI input pin and forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip is able to verify whether the data was correctly received by the non-JTAG chip by reading back the data and comparing to the original data. A status bit or bits are shifted out on a TDO pin and used to determine what data will be shifted in next.
摘要翻译：根据本发明，具有控制器的JTAG兼容芯片具有接收在TDI输入引脚上提供的数据并形成并行地址和数据指令并将数据通过IO引脚传送到非JTAG芯片的控制器，能够验证数据是否为通过读取数据并与原始数据进行比较，由非JTAG芯片正确接收。状态位或位在TDO引脚上移出，用于确定下一个数据将被移位。

2. 发明授权

US06925583B1 Structure and method for writing from a JTAG device with microcontroller to a non-JTAG device 有权
标题翻译：从具有微控制器的JTAG器件写入到非JTAG器件的结构和方法
公开(公告)号：US06925583B1
公开(公告)日：2005-08-02
申请号：US10043637
申请日：2002-01-09
申请人： Arthur H. Khu , Conrad A. Theron , Farshid Shokouhi , Pushpasheel Tawade
发明人： Arthur H. Khu , Conrad A. Theron , Farshid Shokouhi , Pushpasheel Tawade
IPC分类号： G01R31/3185 , G06F11/00
CPC分类号： G01R31/318544 , G01R31/318555
摘要： According to the invention, a JTAG-compliant chip is further provided with a controller that receives data provided on the TDI input pin, forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip without requiring the data to go through the boundary scan register chain of the JTAG-compliant chip. This controller is used to program, erase, and read the other chip. For a non-JTAG flash memory device, the controller in the JTAG-compliant chip generates the necessary programming signal sequences, and applies them to the non-JTAG chip without going through the JTAG boundary scan circuitry.
摘要翻译：根据本发明，JTAG兼容芯片还具有控制器，该控制器接收在TDI输入引脚上提供的数据，形成并行地址和数据指令，并将数据通过IO引脚传送到非JTAG芯片，而不需要数据通过JTAG兼容芯片的边界扫描寄存器链。该控制器用于对其他芯片进行编程，擦除和读取。对于非JTAG闪存器件，JTAG兼容芯片中的控制器产生必要的编程信号序列，并将其应用于非JTAG芯片，而无需通过JTAG边界扫描电路。

3. 发明授权

US07047352B1 Fail-safe method of updating a multiple FPGA configuration data storage system 有权
标题翻译：更新多个FPGA配置数据存储系统的故障安全方法
公开(公告)号：US07047352B1
公开(公告)日：2006-05-16
申请号：US10230920
申请日：2002-08-28
申请人： Arthur H. Khu , Farshid Shokouhi
发明人： Arthur H. Khu , Farshid Shokouhi
IPC分类号： G06F12/00
CPC分类号： G06F17/5054 , G06F11/1441 , G06F12/1425 , H03K19/17764 , H03K19/17772
摘要： Structure and method for updating a system that includes a memory and a programmable logic device (PLD) retains a default PLD configuration in the memory while a new configuration is being stored in the memory, and thus protect the system from failure in case an interruption occurs while the new configuration is being stored. If a power failure interrupts the storing process, the default PLD configuration is still in the memory and can be re-loaded into the PLD and used when the system is re-started to make a further attempt at storing the new configuration. Methods are also disclosed for storing in the memory a configuration for a new PLD before the original PLD is replaced so that system hardware can be updated with minimum effort and disruption, and for dividing a directory structure into protected and unprotected regions.
摘要翻译：用于更新包括存储器和可编程逻辑器件（PLD）的系统的结构和方法在存储器中存储新的配置的同时在存储器中保留默认PLD配置，并且因此在发生中断的情况下保护系统免于故障而新的配置正在被存储。如果电源故障中断存储过程，则默认的PLD配置仍然在存储器中，并且可以重新加载到PLD中，并且当系统重新启动以进一步尝试存储新配置时使用。还公开了用于在原始PLD被替换之前在存储器中存储用于新PLD的配置的方法，使得可以以最小的努力和中断来更新系统硬件，以及将目录结构划分为受保护和不受保护的区域。

4. 发明授权

US07185330B1 Code optimization method and system 有权
标题翻译：代码优化方法和系统
公开(公告)号：US07185330B1
公开(公告)日：2007-02-27
申请号：US09755502
申请日：2001-01-05
申请人： Arthur H. Khu
发明人： Arthur H. Khu
IPC分类号： G06F9/45
CPC分类号： G06F8/4434
摘要： A method and system for optimizing computer source code is provided. Prior to compiling the source code, the code is analyzed to determine the occurrence of repeating patterns of code. The repeating patterns of code are replaced with a programming loop that executes a single instance of the pattern multiple times using appropriate array indices and loop increments. In this manner, source code size is reduced making transfer, storage and compiling more efficient.
摘要翻译：提供了一种优化计算机源代码的方法和系统。在编译源代码之前，分析代码以确定代码重复模式的出现。代码的重复模式被替换为使用适当的数组索引和循环增量多次执行模式的单个实例的编程循环。以这种方式，源代码大小减少，使传输，存储和编译更有效率。

5. 发明授权

US07117341B2 Storing and selecting multiple data streams in distributed memory devices 有权
标题翻译：在分布式存储设备中存储和选择多个数据流
公开(公告)号：US07117341B2
公开(公告)日：2006-10-03
申请号：US11134127
申请日：2005-05-20
申请人： Arthur H. Khu
发明人： Arthur H. Khu
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/023
摘要： Prior art storage techniques have certain limitations, including requiring additional external resources to implement and not making use of all of the available storage space. A method and apparatus using a header table and, in some cases, an alternative access interface are described which allow for more efficient use of available memory space, permit an arbitrary number of data streams to be stored and accessed with a minimal interface, and provide for a simple serial connection to chain multiple memory devices together.
摘要翻译：现有技术的存储技术具有某些限制，包括需要额外的外部资源来实现并且不利用所有可用的存储空间。描述了一种使用报头表的方法和装置，并且在一些情况下描述了替代的访问接口，其允许更有效地使用可用的存储器空间，允许以最小的接口来存储和访问任意数量的数据流，并提供用于简单的串行连接，将多个存储设备链接在一起。

6. 发明授权

US06744388B1 Hardware-friendly general purpose data compression/decompression algorithm 有权
标题翻译：硬件通用数据压缩/解压缩算法
公开(公告)号：US06744388B1
公开(公告)日：2004-06-01
申请号：US10175710
申请日：2002-06-19
申请人： Arthur H. Khu
发明人： Arthur H. Khu
IPC分类号： H03M738
CPC分类号： H03M7/3086
摘要： Methods and systems are provided for dynamically compressing and decompressing a data stream in a manner that facilitates hardware implementation. In one aspect, a compression system identifies literal data sequences of variable length in the data stream and characterizes each literal sequence with an indicator that is inserted into the data stream. Sequences that repeat previous sequences in the data stream are identified and replaced with codes characterizing the repeating sequence. Another aspect provides a decompression method and system for removing indicators inserted by the compression system and replacing codes in the data stream with the repeating sequences characterized by the codes.
摘要翻译：提供了用于以促进硬件实现的方式动态地压缩和解压缩数据流的方法和系统。在一个方面，压缩系统识别数据流中的可变长度的文字数据序列，并用插入到数据流中的指示符来表征每个文字序列。在数据流中重复先前序列的序列被识别并用代表重复序列的代码代替。另一方面提供了一种解压缩方法和系统，用于去除由压缩系统插入的指示符，并用代码表征的重复序列替换数据流中的代码。

7. 发明授权

US5179716A Programmable expandable controller with flexible I/O 失效
标题翻译：可编程可扩展控制器，具有灵活的I / O
公开(公告)号：US5179716A
公开(公告)日：1993-01-12
申请号：US370148
申请日：1989-06-21
申请人： Om P. Agrawal , Arthur H. Khu , William Chen
发明人： Om P. Agrawal , Arthur H. Khu , William Chen
IPC分类号： G06F9/22 , G06F9/26
CPC分类号： G06F9/264 , G06F9/223
摘要： A programmable controller which combines microaddress control logic, memory, a microinstruction decoder, and I/O into a unitary, integrated device. The microaddress control logic is responsive to sequencing signals developed by the microinstruction decoder, and includes an address generator which develops the program address. The memory, which can be either PROM or RAM, is addressed by the address and outputs a microinstruction word to a pipeline register. The microinstruction word has an internal field which is coupled to inputs of the microaddress control logic and the microinstruction decoder, and a control field which is coupled to an output buffer. The output buffer includes multiplexers which permit either the program count or the control field to be multiplexed to the output pins of the device. When the program address is multiplexed to the output pins, the programmable controller can address external memory devices.
摘要翻译：可编程控制器，将微地址控制逻辑，存储器，微指令解码器和I / O组合到一体的集成器件中。微地址控制逻辑响应于由微指令解码器开发的排序信号，并且包括开发程序地址的地址发生器。存储器可以是PROM或RAM，由地址寻址，并将微指令字输出到流水线寄存器。微指令字具有耦合到微地址控制逻辑和微指令解码器的输入的内部场，以及耦合到输出缓冲器的控制场。输出缓冲器包括允许程序计数或控制字段复用到器件的输出引脚的多路复用器。当程序地址复用到输出引脚时，可编程控制器可以寻址外部存储器件。

8. 发明授权

US4963768A Flexible, programmable cell array interconnected by a programmable switch matrix 失效
标题翻译：灵活的可编程单元阵列通过可编程开关矩阵互连
公开(公告)号：US4963768A
公开(公告)日：1990-10-16
申请号：US243574
申请日：1988-09-12
申请人： Om P. Agrawal , Kerry A. Ilgenstein , Michael J. Wright , Jerry D. Moench , Arthur H. Khu
发明人： Om P. Agrawal , Kerry A. Ilgenstein , Michael J. Wright , Jerry D. Moench , Arthur H. Khu
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17708 , H03K19/17728 , H03K19/1774 , H03K19/17744
摘要： A high density segmented programmable array logic device utilizes a switch interconnection matrix to couple an array of programmable logic cells. Each programmable logic cell includes programmable input logic macrocells, programmable feedback logic macrocells, programmable output logic macrocells, buried state logic macrocells and an assembly of programmable AND gates and OR gates. Each input macrocell, output macrocell and buried state macrocell has means for generating either a registered/latched output signal or a combinatorial output signal in response to an input signal to the cell. The various switches are used to couple signals to or from the assembly of programmable AND gates and OR gates.
摘要翻译：高密度分段可编程阵列逻辑器件利用开关互连矩阵耦合可编程逻辑单元阵列。每个可编程逻辑单元包括可编程输入逻辑宏单元，可编程反馈逻辑宏单元，可编程输出逻辑宏单元，埋入状态逻辑宏单元以及可编程与门和或门组合。每个输入宏单元，输出宏单元和掩埋状态宏单元具有用于响应于对单元的输入信号而产生已注册/锁存的输出信号或组合输出信号的装置。各种开关用于将信号耦合到可编程“与”门和“或”门的组合。

9. 发明授权

US07685380B1 Method for using configuration memory for data storage and read operations 有权
标题翻译：使用配置存储器进行数据存储和读取操作的方法
公开(公告)号：US07685380B1
公开(公告)日：2010-03-23
申请号：US11169462
申请日：2005-06-29
申请人： Arthur H. Khu
发明人： Arthur H. Khu
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , H03K19/17748 , H03K19/1776
摘要： Individual storage locations in a PROM that stores a configuration file for a PLD may be directly addressed so that selected portions of the data stored therein may be replaced or updated with new data without having to erase all the contents of the PROM, reprogram the PROM with a new configuration file, and/or reconfigure the FPGA with the new configuration file. For some embodiments, a PROM includes a JTAG-compatible interface that is coupled to a JTAG-compatible test circuit provided within the PLD, and circuit within the PLD is configured to directly address individual storage locations in the PROM via the PROM's JTAG interface using well-known JTAG commands.
摘要翻译：存储PLD配置文件的PROM中的各个存储单元可以被直接寻址，使得存储在其中的数据的所选部分可以用新数据替换或更新，而不必擦除PROM的所有内容，将PROM重新编程为PROM 新配置文件，和/或使用新配置文件重新配置FPGA。对于一些实施例，PROM包括耦合到在PLD内提供的JTAG兼容测试电路的JTAG兼容接口，并且PLD内的电路被配置为经由PROM的JTAG接口使用阱直接地寻址PROM中的各个存储位置已知的JTAG命令。

10. 发明授权

US06912646B1 Storing and selecting multiple data streams in distributed memory devices 有权
公开(公告)号：US06912646B1
公开(公告)日：2005-06-28
申请号：US10337766
申请日：2003-01-06
申请人： Arthur H. Khu
发明人： Arthur H. Khu
IPC分类号： G06F12/00 , G06F12/02 , G11C5/00
CPC分类号： G06F12/023
摘要： Prior art storage techniques have certain limitations, including requiring additional external resources to implement and not making use of all of the available storage space. A method and apparatus using a header table and, in some cases, an alternative access interface are described which allow for more efficient use of available memory space, permit an arbitrary number of data streams to be stored and accessed with a minimal interface, and provide for a simple serial connection to chain multiple memory devices together.

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