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1. 发明授权

US06292860B1 Method for preventing deadlock by suspending operation of processors, bridges, and devices 失效
标题翻译：通过暂停处理器，网桥和设备的操作来防止死锁的方法
公开(公告)号：US06292860B1
公开(公告)日：2001-09-18
申请号：US08991697
申请日：1997-12-16
申请人： Arthur F. Cochcroft, Jr. , Edward A. McDonald , Byron L. Reams , Harry W. Scrivener , Bobby W. Batchler
发明人： Arthur F. Cochcroft, Jr. , Edward A. McDonald , Byron L. Reams , Harry W. Scrivener , Bobby W. Batchler
IPC分类号： G06F1300
CPC分类号： G06F9/524 , G06F13/36 , G06F13/4036
摘要： A deadlock-avoidance system for a computer. In a multi-bus, multi-processor computer, one processor may request a lock on a bus, to execute a locked cycle, thereby blocking all other processors, and other agents, from access to the bus. In addition, a conflicting agent may, in effect, lock a resource which is needed by the processor to complete the cycle for which the lock was requested. These two locks can create a deadlock situation which stalls the computer: the processor and the conflicting agent have each locked a resource needed by the other. Under the invention, when a locked cycle is requested by a processor, all other operations are suspended in the computer. Then queues standing in memory controllers are emptied. If a process requested by an agent occupies a resource, such as a bridge, required by the requested locked cycle, that resource is freed. Then the locked cycle is executed.
摘要翻译：计算机的死锁避免系统。在多总线多处理器计算机中，一个处理器可以请求总线上的锁定，以执行锁定的周期，从而阻止所有其他处理器和其他代理人访问总线。此外，冲突代理实际上可以锁定处理器所需的资源来完成请求锁的周期。这两个锁可能会造成死锁的情况，使计算机停顿：处理器和冲突代理程序都锁定了另一个所需的资源。根据本发明，当处理器请求锁定的周期时，所有其他操作都被挂起在计算机中。然后排在内存控制器中的队列被清空。如果代理所请求的进程占用所请求的锁定周期所需的资源（例如网桥），该资源将被释放。然后执行锁定循环。

2. 发明授权

US6047316A Multiprocessor computing apparatus having spin lock fairness 失效
标题翻译：具有自旋锁公平性的多处理器计算设备
公开(公告)号：US6047316A
公开(公告)日：2000-04-04
申请号：US989617
申请日：1997-12-12
申请人： Richard R. Barton , Arthur F. Cochcroft, Jr. , Edward A. McDonald , Robert J. Miller , Byron L. Reams , Roy M. Stevens , Billy K. Taylor
发明人： Richard R. Barton , Arthur F. Cochcroft, Jr. , Edward A. McDonald , Robert J. Miller , Byron L. Reams , Roy M. Stevens , Billy K. Taylor
IPC分类号： G06F9/46 , G06F12/00
CPC分类号： G06F9/52 , G06F12/0817
摘要： A multiprocessor computing apparatus that includes a mechanism for favoring at least one processor over another processor to achieve more equitable access to cached data. Logic for detecting when, for example, a remote and a local processor are attempting to access data from the cache of another local processor is disclosed. Logic that provides an advantage to the remote processor in a manner that achieves fairer access among the various processors is also disclosed.
摘要翻译：一种多处理器计算装置，其包括用于在另一处理器上有利于至少一个处理器以实现对缓存数据的更公平访问的机制。公开了用于检测例如远程和本地处理器何时尝试从另一本地处理器的高速缓存访问数据的逻辑。还公开了以在各种处理器之间实现更公平的访问的方式为远程处理器提供优势的逻辑。

3. 发明授权

US6026472A Method and apparatus for determining memory page access information in a non-uniform memory access computer system 失效
标题翻译：用于在不均匀的存储器访问计算机系统中确定存储器页面访问信息的方法和装置
公开(公告)号：US6026472A
公开(公告)日：2000-02-15
申请号：US881413
申请日：1997-06-24
申请人： Larry C. James , Arthur F. Cochcroft, Jr. , Peter Washington , Edward A. McDonald
发明人： Larry C. James , Arthur F. Cochcroft, Jr. , Peter Washington , Edward A. McDonald
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0813 , G06F2212/2542
摘要： A hardware method to concurrently obtain memory access locality information for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within the shared system memory. Whenever the processing node generates a transaction requiring access to a memory address within system memory, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. Thus, a record of memory access patterns is created which can be used to optimize memory and process assignments in the computer system.
摘要翻译：为了优化包括分布式系统存储器在内的多节点NUMA架构计算机系统中的存储器和处理分配的目的，同时获得用于系统存储器（页）的大量连续部分的存储器访问位置信息的硬件方法。页面访问监视逻辑包含在包含共享系统存储器的一部分的每个处理节点内。该页面访问监视逻辑维护多个页面访问计数器，每个页面访问计数器对应于共享系统存储器内的不同存储器页面地址。每当处理节点产生需要访问系统存储器内的存储器地址的事务时，页面访问监视逻辑增加与寻求访问的存储器地址相对应的页面访问计数器中的计数值。因此，创建了可用于优化计算机系统中的存储器和处理分配的存储器访问模式的记录。

4. 发明授权

US5359715A Architectures for computer systems having multiple processors, multiple system buses and multiple I/O buses interfaced via multiple ported interfaces 失效
标题翻译：具有多个处理器，多个系统总线和多个I / O总线的计算机系统架构，通过多个端口接口连接
公开(公告)号：US5359715A
公开(公告)日：1994-10-25
申请号：US760786
申请日：1991-09-16
申请人： Thomas F. Heil , Craig A. Walrath , Jimmy D. Pike , Edward A. McDonald , Arthur F. Cochcroft, Jr. , P. Chris Raeuber , Daniel C. Robbins , Gene F. Young
发明人： Thomas F. Heil , Craig A. Walrath , Jimmy D. Pike , Edward A. McDonald , Arthur F. Cochcroft, Jr. , P. Chris Raeuber , Daniel C. Robbins , Gene F. Young
IPC分类号： G06F15/16 , G06F13/24 , G06F13/36 , G06F15/177 , G06F13/00
CPC分类号： G06F13/24
摘要： Multiple processor systems are configured to include at least two system or memory buses with at least two processors coupled to each of the system buses, and at least two I/O buses which are coupled to the system buses to provide multiple expansion slots hosting up to a corresponding number of I/O bus agents for the systems at the cost of a single system bus load for each I/O bus. Each of the system and I/O buses are independently arbitrated to define decoupled bus systems for the multiple processor systems of the present invention. Main memory for the systems is made up of at least two memory interleaves, each of which can be simultaneously accessed through the system buses. Each of the I/O buses are interfaced to the system buses by an I/O interface circuit which buffers data written to and read from the main memory or memory interleaves by I/O bus agents.
摘要翻译：多处理器系统被配置为包括至少两个系统或存储器总线，其中至少两个处理器耦合到每个系统总线，以及耦合到系统总线的至少两个I / O总线，以提供多个扩展槽，为每个I / O总线以单个系统总线负载为代价的系统的相应数量的I / O总线代理。系统和I / O总线中的每一个被独立地仲裁以定义用于本发明的多个处理器系统的解耦总线系统。用于系统的主存储器由至少两个存储器交错组成，每个存储器交错可以通过系统总线同时访问。每个I / O总线通过I / O接口电路连接到系统总线，I / O接口电路缓冲写入主存储器的数据或由I / O总线代理器读取存储器交错的数据。

5. 发明授权

US6058475A Booting method for multi-processor computer 失效
标题翻译：多处理器计算机的启动方式
公开(公告)号：US6058475A
公开(公告)日：2000-05-02
申请号：US935910
申请日：1997-09-22
申请人： Edward A. McDonald , Bobby W. Batchler
发明人： Edward A. McDonald , Bobby W. Batchler
IPC分类号： G06F11/00 , G06F15/177
CPC分类号： G06F11/1417 , G06F15/177
摘要： A system for booting a multi-processor computer. If a normal boot attempt fails, different processors are selected, one-at-a-time, for performing the boot routine. During the boot routing, all other processors are held inactive. After boot, processors are tested for health. Non-healthy processors are held inactive, and healthy processors are activated as usual.
摘要翻译：用于启动多处理器计算机的系统。如果正常启动尝试失败，则会一次一个地选择不同的处理器来执行引导例程。在引导路由期间，所有其他处理器保持不活动。引导后，处理器进行健康测试。非健康的处理器保持不活动状态，健康的处理器照常激活。

6. 发明授权

US5758065A System and method of establishing error precedence in a computer system 失效
标题翻译：在计算机系统中建立错误优先的系统和方法
公开(公告)号：US5758065A
公开(公告)日：1998-05-26
申请号：US565520
申请日：1995-11-30
申请人： Byron L. Reams , Edward A. McDonald
发明人： Byron L. Reams , Edward A. McDonald
IPC分类号： G06F11/07 , G06F11/00
CPC分类号： G06F11/0745 , G06F11/0724 , G06F11/079
摘要： A system and method of establishing error precedence in a computer system which determine a first error to occur. The system determines the order of occurrence of errors in a computer system and includes error precedence modules which record and order errors that occur on a first bus with error that occur on a second bus. Diagnostic processing circuitry reads the errors stored within the error precedence modules and their order of occurrence and determines which bus the first error occurred on.
摘要翻译：一种在计算机系统中建立错误优先级的系统和方法，其确定发生第一错误。系统确定计算机系统中错误发生的顺序，并且包括错误优先模块，其记录和排序在第二总线上发生错误的第一总线上发生的错误。诊断处理电路读取错误优先模块中存储的错误及其出现顺序，并确定发生第一个错误的总线。

7. 发明授权

US6073216A System and method for reliable system shutdown after coherency corruption 失效
标题翻译：一致性损坏后可靠系统关机的系统和方法
公开(公告)号：US6073216A
公开(公告)日：2000-06-06
申请号：US980882
申请日：1997-11-25
申请人： Edward A. McDonald , James M. Ottinger , Harry W. Scrivener
发明人： Edward A. McDonald , James M. Ottinger , Harry W. Scrivener
IPC分类号： G06F11/07 , G06F11/10 , G06F12/08
CPC分类号： G06F11/073 , G06F11/0724 , G06F11/0793 , G06F12/0817 , G06F11/1064
摘要： There is disclosed a memory control circuit for use in a processing system containing a plurality of processors coupled to a main memory by a common bus. The memory control circuit is adapted for implementing directory-based coherency in the processing system according to a selected coherency algorithm and comprises: 1) monitoring circuitry for detecting coherency corruption in a coherency directory associated with the main memory; and 2) coherency control circuitry responsive to a detection of coherency corruption in the coherency directory for dynamically modifying the selected coherency algorithm, thereby enabling the processing system to shut down in a controlled manner. In some embodiments, the monitoring circuitry further detects possible system coherency failure conditions external to the coherency directory and the coherency control circuitry responds to the detection of a possible system coherency failure condition by dynamically modifying the selected coherency algorithm, thereby enabling the processing system to shut down in a controlled manner.
摘要翻译：公开了一种用于处理系统中的存储器控制电路，该处理系统包含通过公共总线耦合到主存储器的多个处理器。存储器控制电路适于根据所选择的一致性算法在处理系统中实现基于目录的一致性，并且包括：1）监视电路，用于检测与主存储器相关联的一致性目录中的一致性损坏; 以及2）相干性控制电路，其响应于所述一致性目录中的一致性损坏的检测，以动态地修改所选择的一致性算法，从而使所述处理系统能够以受控的方式关闭。在一些实施例中，监视电路还检测相干目录外的可能的系统一致性故障条件，并且一致性控制电路通过动态地修改所选择的一致性算法来响应可能的系统一致性故障条件的检测，从而使处理系统能够关闭以受控的方式下来。

8. 发明授权

US6012127A Multiprocessor computing apparatus with optional coherency directory 失效
标题翻译：具有可选一致性目录的多处理器计算设备
公开(公告)号：US6012127A
公开(公告)日：2000-01-04
申请号：US989371
申请日：1997-12-12
申请人： Edward A. McDonald , James M. Ottinger , Harry W. Scrivener, III
发明人： Edward A. McDonald , James M. Ottinger , Harry W. Scrivener, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0831
摘要： A multiprocessor computing apparatus including a plurality of processors each having a cache memory and preferably arranged in nodes on a system bus. A first cache coherency providing mechanism coupled to the processors for achieving system level cache coherency. A second cache coherency providing mechanism is also provided. When an error is detected in the first cache coherency providing mechanism, this mechanism is disabled and cache coherency is achieved by the second cache coherency providing mechanism. In a preferred embodiment, the first mechanism includes coherency directories and the second mechanism includes bus snooping.
摘要翻译：一种多处理器计算装置，包括多个处理器，每个处理器具有高速缓冲存储器，并且优选地布置在系统总线上的节点中。耦合到处理器的第一高速缓存一致性提供机制，用于实现系统级高速缓存一致性。还提供了第二高速缓存一致性提供机制。当在第一高速缓存一致性提供机制中检测到错误时，该机制被禁用，并且由第二高速缓存一致性提供机制实现高速缓存一致性。在优选实施例中，第一机制包括相干目录，第二机制包括总线监听。

9. 发明授权

US06098113A Apparatus and method for address translation and allocation for a plurality of input/output (I/O) buses to a system bus 失效
标题翻译：用于多个输入/输出（I / O）总线到系统总线的地址转换和分配的装置和方法
公开(公告)号：US06098113A
公开(公告)日：2000-08-01
申请号：US417701
申请日：1995-04-06
申请人： Thomas F. Heil , Edward A. McDonald , James M. Ottinger , Jeffrey A. Hawkey
发明人： Thomas F. Heil , Edward A. McDonald , James M. Ottinger , Jeffrey A. Hawkey
IPC分类号： G06F13/42 , G06F3/00
CPC分类号： G06F13/423
摘要： Multiple subsystem I/O (Input/Output) buses are coupled to one or more system buses of a computer system by interface circuits which perform necessary decoding of memory space and I/O (Input/Output) space for allocation of portions of the memory space and the I/O (Input/Output) space to each I/O (Input/Output) bus. The interface circuits also translate fixed addresses within each I/O (Input/Output) bus to permit proper operation of the I/O (Input/Output) buses with the computer system. The interface circuits are programmed by the computer system to define the allocated memory spaces and I/O (Input/Output) spaces for the corresponding I/O (Input/Output) buses. Programming of the I/O (Input/Output) buses is performed at the time of system configuration by writing appropriate values into configuration registers incorporated into each of the interface circuits.
摘要翻译：多个子系统I / O（输入/输出）总线通过接口电路耦合到计算机系统的一个或多个系统总线，所述接口电路执行存储器空间的必要解码以及用于分配存储器部分的I / O（输入/输出）空间和每个I / O（输入/输出）总线的I / O（输入/输出）空间。接口电路还可以转换每个I / O（输入/输出）总线中的固定地址，以允许计算机系统正确操作I / O（输入/输出）总线。接口电路由计算机系统编程，以便为相应的I / O（输入/输出）总线定义分配的存储空间和I / O（输入/输出）空间。通过将合适的值写入并入每个接口电路的配置寄存器中，在系统配置时执行I / O（输入/输出）总线的编程。

10. 发明授权

US6120535A Microporous tubular prosthesis 失效
标题翻译：微孔管状假体
公开(公告)号：US6120535A
公开(公告)日：2000-09-19
申请号：US975584
申请日：1997-11-21
申请人： Edward A. McDonald , Michael Henson , Joe W. Young
发明人： Edward A. McDonald , Michael Henson , Joe W. Young
IPC分类号： A61F2/00 , A61F2/82 , A61F2/92 , A61N5/10
CPC分类号： A61F2/962 , A61F2/92 , A61F2/0077 , A61F2002/826 , A61F2002/8483 , A61F2002/9517 , A61F2210/0076 , A61F2210/0095 , A61F2220/005 , A61F2220/0075 , A61F2250/0067 , A61N5/1002
摘要： Disclosed is a tubular microporous prosthesis formed by rolling a flexible sheet around a longitudinal axis. Preferably, the prosthesis is self expandable under the radially outwardly directed spring bias of the rolled sheet. At least a portion of the sheet may be provided with a coating to affect the physical and/or biological properties of the prosthesis.
摘要翻译：公开了一种通过围绕纵向轴线滚动柔性片而形成的管状微孔假体。优选地，假体在轧制板的径向向外指向的弹簧偏压下是可自膨的。片材的至少一部分可以设置有涂层以影响假体的物理和/或生物学性质。

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