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1. 发明授权

US06225936B1 Direct digital downconverter and method for converting an analog signal to a digital signal 失效
标题翻译：直接数字下变频器和将模拟信号转换为数字信号的方法
公开(公告)号：US06225936B1
公开(公告)日：2001-05-01
申请号：US09326073
申请日：1999-06-04
申请人： Arnold H. Silver , Dale J. Durand , Peter L. McAdam
发明人： Arnold H. Silver , Dale J. Durand , Peter L. McAdam
IPC分类号： H03M100
CPC分类号： H03M1/60
摘要： A control scheme for operating an oscillator/counter A/D converter so that it simultaneously provides frequency downconversion, band pass filtering and analog-to-digital conversion of an analog signal, where the analog signal includes a carrier wave modulated with information by any known modulation technique. The converter uses a superconducting, Josephson single flux quantum circuit operating as a voltage controlled oscillator. The voltage controlled oscillator receives the analog signal to be converted, and generates a series of sharp, high frequency pulses based on the characteristics of the carrier signal. The series of pulses are applied to a gate circuit that, depending on a gate control signal, either blocks the pulses or passes the pulses to either an increment or a decrement port of a digital counter. When the pulses are passed by the gate circuit, the counter circuit accumulates the pulses during a sampling period. The sampling period covers a range of gate control pulses so that the accumulation of pulses defines consecutive on/off periods of the gate control signal. The scheme provides for frequency conversion and eliminating or minimizing the amount of DC response present in the digital output signal.
摘要翻译：一种用于操作振荡器/计数器A / D转换器的控制方案，以便它同时提供模拟信号的下变频，带通滤波和模数转换，其中模拟信号包括通过任何已知的信息由信息调制的载波调制技术。该转换器使用作为压控振荡器工作的超导约瑟夫森单通量量子电路。压控振荡器接收要转换的模拟信号，并且基于载波信号的特性产生一系列尖锐的高频脉冲。脉冲序列被施加到门电路，门电路根据门控制信号阻塞脉冲或将脉冲传递到数字计数器的增量或递减端口。当脉冲通过门电路时，计数器电路在采样周期内累积脉冲。采样周期覆盖一个栅极控制脉冲的范围，使得脉冲的累积定义了栅极控制信号的连续的开/关周期。该方案提供频率转换，并消除或最小化数字输出信号中存在的直流响应的数量。

2. 发明授权

US5942997A Correlated superconductor single flux quantum analog-to-digital converter 失效
标题翻译：相关超导单通量子模拟数字转换器
公开(公告)号：US5942997A
公开(公告)日：1999-08-24
申请号：US920741
申请日：1997-08-29
申请人： Arnold H. Silver , Dale J. Durand
发明人： Arnold H. Silver , Dale J. Durand
IPC分类号： G01R33/035 , H03M1/12 , H03M1/44 , H03M1/60
CPC分类号： H03M1/121 , H03M1/60
摘要： A correlated superconductor single flux quantum oscillator-counter analog-to-digital (A/D) converter has a superconducting quantum interference device (SQUID) quantizer 20 with two Josephson junctions 24 and 26, each connected to a digital sampling and counting circuit with synchronized timing to increase the sampling rate or the bit resolution of the A/D converter. In a preferred embodiment, a plurality of SQUID quantizers 60 . . . 72 each with two Josephson junctions 74 . . . 88 are connected to a counter structure with precisely synchronized timing to further increase the sampling frequency and/or the bit resolution. A counter structure preferably comprises multiple rows 218, 240, 254 of single flux quantum flip-flops 220 . . . 234, 242 . . . 248, 256, 258 and parallel-serial converter/shift registers 236 250, 260 to produce an output digital data stream in serial form.
摘要翻译：相关超导单通量量子振荡器 - 计数器模数（A / D）转换器具有一个超导量子干涉装置（SQUID）量化器20，其具有两个约瑟夫逊结24和26，每个连接到数字采样和计数电路，同步定时增加A / D转换器的采样率或位分辨率。在优选实施例中，多个SQUID量化器60。。。每个都有两个约瑟夫逊路口74。。。 88以精确同步的定时连接到计数器结构，以进一步增加采样频率和/或比特分辨率。计数器结构优选地包括单通量量子触发器220的多行218,240,254。。。 234,242。。。 248,256,258和并行 - 串行转换器/移位寄存器236 250,260，以产生串行形式的输出数字数据流。

3. 发明授权

US6127960A Direct digital downconverter based on an oscillator/counter analog-to-digital converter 失效
标题翻译：基于振荡器/计数器模数转换器的直接数字下变频器
公开(公告)号：US6127960A
公开(公告)日：2000-10-03
申请号：US127020
申请日：1998-07-31
申请人： Arnold H. Silver , Dale J. Durand
发明人： Arnold H. Silver , Dale J. Durand
IPC分类号： H03B5/02 , H03D7/12 , H03M1/60 , H04L27/00
CPC分类号： H03D7/12 , H03M1/60
摘要： A control scheme for operating an oscillator/counter A/D converter (10) so that it simultaneously provides frequency downconversion, band pass filtering and analog-to-digital conversion of an analog signal, where the analog signal includes a carrier wave modulated with information by any known modulation technique. The converter (10) uses a superconducting, Josephson single flux quantum circuit operating as a voltage controlled oscillator (12). The voltage controlled oscillator (12) receives the analog signal to be converted, and generates a series of sharp, high frequency pulses based on the characteristics of the carrier signal. The series of pulses are applied to a gate circuit (14) that either passes or blocks the pulses depending on a gate control signal. When the pulses are passed by the gate circuit (14), a counter circuit (16) accumulates the pulses during a sampling period. The sampling period covers a range of gate control pulses so that the accumulation of pulses defines consecutive on/off periods of the gate control signal. Each time the gate control signal passes the pulses from the variable controlled oscillator (12), the converter (10) effectively performs a bit multiplication that gives the frequency conversion.
摘要翻译：一种用于操作振荡器/计数器A / D转换器（10）的控制方案，以便它同时提供模拟信号的下变频，带通滤波和模数转换，其中模拟信号包括用信息调制的载波通过任何已知的调制技术。转换器（10）使用作为压控振荡器（12）工作的超导约瑟夫逊单通量量子电路。压控振荡器（12）接收要转换的模拟信号，并且基于载波信号的特性产生一系列尖锐的高频脉冲。脉冲序列被施加到门电路（14），门电路（14）根据门控信号通过或阻塞脉冲。当脉冲通过门电路（14）时，计数器电路（16）在采样周期内累积脉冲。采样周期覆盖一个栅极控制脉冲的范围，使得脉冲的累积定义了栅极控制信号的连续的开/关周期。每当栅极控制信号通过来自可变控制振荡器（12）的脉冲时，转换器（10）有效执行给出频率转换的位乘法。

4. 发明授权

US5916848A Self-aligned thin barrier high temperature superconductor edge junction 失效
公开(公告)号：US5916848A
公开(公告)日：1999-06-29
申请号：US947342
申请日：1997-10-08
申请人： Dale J. Durand
发明人： Dale J. Durand
IPC分类号： H01L39/22 , H01L39/24
CPC分类号： H01L39/2496 , H01L39/225 , Y10S505/702
摘要： An edge junction 10 with reduced parasitic inductance. The edge junction 10 has a laminar structure 22 including: a substrate 14; a first superconductive layer 12 deposited on a substrate 14; a first dielectric layer 16 deposited on the first superconductive layer 12; a second superconductive layer 18 deposited on the first dielectric layer 16; and a second dielectric layer 20 deposited on the second superconductive layer 18. The first and second superconductive layers 12 and 18 and the first and second dielectric layers 16 and 20 form a first laminar structure 22 having a planar segment 24 and a self-aligned ramp segment 26, the ramp segment 26 having a constantly-decreasing thickness and being connected to the planar segment 24 at an angle .theta. thereto. The edge junction 10 further includes a barrier layer 28 deposited on the first laminar structure 22; and a third superconductive layer 30 deposited on the barrier layer 28 to form: (i) a first Josephson junction 32 at the ramp segment 26 proximate the first superconductive layer 12 and (ii) a second Josephson junction 34 at the ramp segment 26 proximate the second superconductive layer 18. The overlap area of the first and the third superconductive layers 12 and 30 is greater than the overlap area of the second and the third superconductive layers 18 and 30, whereby the inductive parasitic effect of the first Josephson junction 32 on the second Josephson junction 34 is reduced. The superconductive layers 12, 18 and 30 are epitaxial with a c-axis in a direction substantially normal to the plane of the planar segment 24.

5. 发明授权

US06750794B1 Application of single flux quantum pulse interaction to the simultaneous sampling in-phase and quadrature analog-to-digital converter 失效
标题翻译：应用单通量量子脉冲相互作用到同步采样同相和正交模数转换器
公开(公告)号：US06750794B1
公开(公告)日：2004-06-15
申请号：US10429479
申请日：2003-05-05
申请人： Dale J. Durand , Quentin P. Herr , Mark W. Johnson
发明人： Dale J. Durand , Quentin P. Herr , Mark W. Johnson
IPC分类号： H03M100
CPC分类号： H03M1/62
摘要： A superconducting oscillator/counter analog-to-digital converter (50) that provides simultaneous in-phase and quadrature-phase of an RF input signal. The RF input signal is converted to a series of SFQ input pulses by a superconducting voltage controlled oscillator (12). A clock circuit (26) generates a series of SFQ clock pulses. The SFQ input pulses and the SFQ clock pulses are applied to a pulse repulsion circuit (52) that outputs the SFQ input pulses and the SFQ clock pulses spaced apart in time. In one embodiment, the pulse repulsion circuit (52) includes two Josephson transmission lines (60, 62), where the magnetic coupling between the lines (60, 62) provides the SFQ pulse repulsion.
摘要翻译：一种提供RF输入信号的同相和正交相位的超导振荡器/计数器模数转换器（50）。 RF输入信号由超导压控振荡器（12）转换成一系列SFQ输入脉冲。时钟电路（26）产生一系列SFQ时钟脉冲。 SFQ输入脉冲和SFQ时钟脉冲被施加到输出SFQ输入脉冲和SFQ时钟脉冲在时间上间隔开的脉冲排斥电路（52）。在一个实施例中，脉冲排斥电路（52）包括两个约瑟夫逊传输线（60,62），其中线路（60,62）之间的磁耦合提供SFQ脉冲排斥。

6. 发明授权

US5939730A Self-aligned thin barrier high temperature superconductor edge junction 失效
标题翻译：自对准薄壁高温超导体边缘结
公开(公告)号：US5939730A
公开(公告)日：1999-08-17
申请号：US743647
申请日：1996-11-04
申请人： Dale J. Durand , Kei F. Lau
发明人： Dale J. Durand , Kei F. Lau
IPC分类号： H01L39/22 , H01L39/24
CPC分类号： H01L39/2496 , H01L39/225 , Y10S505/702
摘要： An edge junction 10 with reduced parasitic inductance. The edge junction 10 has a laminar structure 22 including: a substrate 14; a first superconductive layer 12 deposited on a substrate 14; a first dielectric layer 16 deposited on the first superconductive layer 12; a second superconductive layer 18 deposited on the first dielectric layer 16; and a second dielectric layer 20 deposited on the second superconductive layer 18. The first and second superconductive layers 12 and 18 and the first and second dielectric layers 16 and 20 form a first laminar structure 22 having a planar segment 24 and a self-aligned ramp segment 26, the ramp segment 26 having a constantly-decreasing thickness and being connected to the planar segment 24 at an angle .theta. thereto. The edge junction 10 further includes a barrier layer 28 deposited on the first laminar structure 22; and a third superconductive layer 30 deposited on the barrier layer 28 to form: (i) a first Josephson junction 32 at the ramp segment 26 proximate the first superconductive layer 12 and (ii) a second Josephson junction 34 at the ramp segment 26 proximate the second superconductive layer 18. The overlap area of the first and the third superconductive layers 12 and 30 is greater than the overlap area of the second and the third superconductive layers 18 and 30, whereby the inductive parasitic effect of the first Josephson junction 32 on the second Josephson junction 34 is reduced. The superconductive layers 12, 18 and 30 are epitaxial with a c-axis in a direction substantially normal to the plane of the planar segment 24.
摘要翻译：具有降低的寄生电感的边缘结10。边缘接合部10具有层状结构22，其包括：基板14; 沉积在基板14上的第一超导层12; 沉积在第一超导层12上的第一介电层16; 沉积在第一介电层16上的第二超导层18; 以及沉积在第二超导层18上的第二电介质层20.第一和第二超导层12和18以及第一和第二电介质层16和20形成第一层状结构22，其具有平面段24和自对准斜面段26，斜坡段26具有恒定减小的厚度并且以角度θ连接到平面段24。边缘结10还包括沉积在第一层状结构22上的阻挡层28; 和沉积在阻挡层28上的第三超导层30，以形成：（i）靠近第一超导层12的斜坡段26处的第一约瑟夫逊结32和（ii）在斜坡段26附近的第二约瑟夫逊结34 第二超导层18.第一和第三超导层12和30的重叠面积大于第二和第三超导层18和30的重叠面积，由此第一约瑟夫逊结32的感应寄生效应在第二个约瑟夫逊结34被减少。超导层12,18和30在基本上垂直于平面段24的平面的方向上以c轴外延。

7. 发明授权

US06483339B1 Single flux quantum series biasing technique using superconducting DC transformer 有权
标题翻译：使用超导直流变压器的单通量子量子偏置技术
公开(公告)号：US06483339B1
公开(公告)日：2002-11-19
申请号：US09935310
申请日：2001-08-22
申请人： Dale J. Durand , Quentin P. Herr , Mark W. Johnson
发明人： Dale J. Durand , Quentin P. Herr , Mark W. Johnson
IPC分类号： H03K19195
CPC分类号： H03K19/1952
摘要： The level of bias current (12) required by a superconductor integrated circuit (2 & 4) is lowered by separating the circuit into portions having separate ground planes and supplying the bias current to the circuit portion (2) in one ground plane in series (10) with that for the circuit portion (4) in another ground plane. To maintain DC isolation between those circuit portions, SFQ pulses inputted (SFQ IN) move across the separate ground planes through a pair of inductively coupled SQUIDS (3 & 5) that define a DC transformer; and a combiner (7) reconstitutes and outputs the SFQ pulses. To provide inductive coupling the DC transformer includes a primary (25) and isolated secondary (5) winding.
摘要翻译：通过将电路分离成具有分离的接地平面的部分并将偏置电流提供给串联的一个接地平面中的电路部分（2）来降低超导体集成电路（2和4）所需的偏置电流（12）的电平（ 10）与电路部分（4）在另一个接地平面中的电路部分。为了保持这些电路部分之间的直流隔离，输入的SFQ脉冲（SFQ IN）通过一对感应耦合的SQUIDS（3和5）在独立的接地层上移动，定义了一个直流变压器; 并且组合器（7）重构并输出SFQ脉冲。为了提供电感耦合，DC变压器包括初级（25）和隔离次级（5）绕组。

8. 发明授权

US06388600B1 Asynchronous superconductor serial multiply-accumulator 失效
标题翻译：异步超导体串联倍增器
公开(公告)号：US06388600B1
公开(公告)日：2002-05-14
申请号：US09711322
申请日：2000-11-13
申请人： Mark W. Johnson , Dale J. Durand
发明人： Mark W. Johnson , Dale J. Durand
IPC分类号： H03M112
CPC分类号： H03M1/60
摘要： An oscillator/multiply-accumulator AID converter (100) which simultaneously provides frequency downconversion, band pass filtering and analog-to-digital conversion of an analog signal, where the analog signal includes a carrier wave modulated with information by any known modulation technique. The converter (100) uses a superconducting, Josephson single flux quantum circuit operating as a voltage controlled oscillator (102). The voltage controlled oscillator (102) receives the analog signal to be converted, and generates a series of sharp, high frequency pulses based on the characteristics of the carrier signal. The series of pulses are applied to a gate circuit (104) that either passes or blocks the pulses depending on a gate control signal (103). When the pulses are passed by the gate circuit (104), a multiply-accumulator (106) multiplies the pulse by a binary coefficient (109) and accumulates the products (111) resulting from the multiplication during a predetermined time period. The predetermined time period includes at least one sampling period. Each sample is multiplied by a different weight and their products (111) are accumulated. This operation eliminates the DC response, and leads to an improved frequency response.
摘要翻译：同时提供模拟信号的频率下变频，带通滤波和模数转换的振荡器/乘法器AID转换器（100），其中模拟信号包括通过任何已知调制技术用信息调制的载波。转换器（100）使用作为压控振荡器（102）工作的超导约瑟夫森单通量量子电路。压控振荡器（102）接收要转换的模拟信号，并且基于载波信号的特性产生一系列尖锐的高频脉冲。脉冲序列被施加到门电路（104），门电路（104）根据门控信号（103）通过或阻塞脉冲。当脉冲被门电路（104）通过时，乘法累加器（106）将脉冲乘以二进制系数（109），并且在预定时间段内积累乘积产生的乘积（111）。预定时间段包括至少一个采样周期。每个样品乘以不同的重量，并且其产物（111）被累积。该操作消除了直流响应，并且导致了改进的频率响应。

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