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1. 发明申请

US20210295140A1 NEURAL NETWORK PROCESSING 有权
公开(公告)号：US20210295140A1
公开(公告)日：2021-09-23
申请号：US16826586
申请日：2020-03-23
申请人： Arm Limited
发明人： Rune Holm , John Wakefield Brothers, III
IPC分类号： G06N3/063 , G06F7/50 , G06F7/523 , G06F7/535 , G06F17/18
摘要： A neural network processor is disclosed that includes a combined convolution and pooling circuit that can perform both convolution and pooling operations. The circuit can perform a convolution operation by a multiply circuit determining products of corresponding input feature map and convolution kernel weight values, and an add circuit accumulating the products determined by the multiply circuit in storage. The circuit can perform an average pooling operation by the add circuit accumulating input feature map data values in the storage, a divisor circuit determining a divisor value, and a division circuit dividing the data value accumulated in the storage by the determined divisor value. The circuit can perform a maximum pooling operation by a maximum circuit determining a maximum value of input feature map data values, and storing the determined maximum value in the storage.

2. 发明授权

US12001369B2 Broadcast regions for multi-processor arrangement 有权
公开(公告)号：US12001369B2
公开(公告)日：2024-06-04
申请号：US17709293
申请日：2022-03-30
申请人： Arm Limited
发明人： Erik Persson , Graeme Leslie Ingram , Rune Holm , John Wakefield Brothers, III
IPC分类号： G06F13/42 , G06N5/04
CPC分类号： G06F13/42 , G06N5/04
摘要： The present disclosure relates generally to multi-processor arrangements and, more particularly, to broadcast regions for multi-processor arrangements.

3. 发明公开

US20230315670A1 BROADCAST REGIONS FOR MULTI-PROCESSOR ARRANGEMENT 审中-公开
公开(公告)号：US20230315670A1
公开(公告)日：2023-10-05
申请号：US17709293
申请日：2022-03-30
申请人： Arm Limited
发明人： Erik Persson , Graeme Leslie Ingram , Rune Holm , John Wakefield Brothers, III
IPC分类号： G06F13/42 , G06N5/04
CPC分类号： G06F13/42 , G06N5/04
摘要： The present disclosure relates generally to multi-processor arrangements and, more particularly, to broadcast regions for multi-processor arrangements.

4. 发明申请

US20210303992A1 EXECUTING NEURAL NETWORKS ON ELECTRONIC DEVICES 有权
公开(公告)号：US20210303992A1
公开(公告)日：2021-09-30
申请号：US16836408
申请日：2020-03-31
申请人： Arm Limited
发明人： John Wakefield Brothers, III
IPC分类号： G06N3/08 , G06N3/04
摘要： When performing neural network processing, the order in which the neural network processing is to be performed is determined, and the order in which weight values to be used for the neural network processing will be used is determined based on the determined order of the neural network processing. The weight values are then provided to the processor that is to perform the neural network processing in the determined order for the weight values, with the processor, when performing the neural network processing, then using the weight values in the determined order that they are provided to the processor.

5. 发明公开

US20240345903A1 DATA PROCESSING APPARATUS AND METHODS TENSOR TRANSFORM OPERATION 审中-公开
公开(公告)号：US20240345903A1
公开(公告)日：2024-10-17
申请号：US18298833
申请日：2023-04-11
申请人： Arm Limited
发明人： John Wakefield Brothers, III , Derek David Whiteman
IPC分类号： G06F9/54
CPC分类号： G06F9/544
摘要： The present disclosure relates to a data processing apparatus for a processing resource to perform a transform operation on an input tensor for the processing resource, said input tensor being formed of a plurality of blocks, each block being a portion of said input tensor capable of being operated on independently of each other, said data processing apparatus comprising: communication circuitry to communicate with a control module and a shared storage of said processing resource; processing circuitry to perform said transform operation, said processing circuitry comprising sub-block processing circuitry and transformation circuitry; and a local storage to store transform operation output from said processing circuitry; wherein said communication circuitry is configured to: receive one or more transform parameters; read a first input sub-block from said shared storage, said first input sub-block being a portion of a first block of said input tensor corresponding to a processing unit of said processing circuitry; and write a first output sub-block to said shared storage, wherein said sub-block processing circuitry is configured to: divide said first block of said input tensor into one or more input sub-blocks capable of being operated on independently of each other based on said one or more transform parameters; and wherein said transformation circuitry is configured to: perform said transform operation on said first input sub-block based on said one or more transform parameters to generate said first output sub-block; and write said first output sub-block to said local storage.

6. 发明授权

US12061967B2 Processing data for a layer of a neural network 有权
公开(公告)号：US12061967B2
公开(公告)日：2024-08-13
申请号：US17132750
申请日：2020-12-23
申请人： Arm Limited
发明人： John Wakefield Brothers, III , Kartikeya Bhardwaj , Alexander Eugene Chalfin , Danny Daysang Loh
IPC分类号： G06N3/0464 , G06N3/04 , G06N3/08
CPC分类号： G06N3/04 , G06N3/0464 , G06N3/08
摘要： A method of processing input data for a given layer of a neural network using a data processing system comprising compute resources for performing convolutional computations is described. The input data comprises a given set of input feature maps, IFMs, and a given set of filters. The method comprises generating a set of part-IFMs including pluralities of part-IFMs which correspond to respective IFMs, of the given set of IFMs. The method further includes grouping part-IFMs in the set of part-IFMs into a set of selections of part-IFMs. The method further includes convolving, by respective compute resources of the data processing system, the set of selections with the given set of filters to compute a set of part-output feature maps. A data processing system for processing input data for a given layer of a neural network is also described.

7. 发明授权

US11561795B2 Accumulating data values and storing in first and second storage devices 有权
公开(公告)号：US11561795B2
公开(公告)日：2023-01-24
申请号：US16834833
申请日：2020-03-30
申请人： Arm Limited
发明人： Jens Olson , John Wakefield Brothers, III , Jared Corey Smolens , Chi-wen Cheng , Daren Croxford , Sharjeel Saeed , Dominic Hugo Symes
IPC分类号： G06F9/30 , G06F9/38 , G06F9/345 , G06F7/499 , G06F7/57
摘要： Herein described is a method of operating an accumulation process in a data processing apparatus. The accumulation process comprises a plurality of accumulations which output a respective plurality of accumulated values, each based on a stored value and a computed value generated by a data processing operation. The method comprises storing a first accumulated value, the first accumulated value being one of said plurality of accumulated values, into a first storage device comprising a plurality of single-bit storage elements; determining that a predetermined trigger has been satisfied with respect to the accumulation process; and in response to the determining, storing at least a portion of a second accumulated value, the second accumulated value being one of said plurality of accumulated values, into a second storage device.

8. 发明授权

US11537860B2 Neural net work processing 有权
公开(公告)号：US11537860B2
公开(公告)日：2022-12-27
申请号：US16826586
申请日：2020-03-23
申请人： Arm Limited
发明人： Rune Holm , John Wakefield Brothers, III
IPC分类号： G06N3/063 , G06F7/50 , G06F17/18 , G06F7/535 , G06F7/523
摘要： A neural network processor is disclosed that includes a combined convolution and pooling circuit that can perform both convolution and pooling operations. The circuit can perform a convolution operation by a multiply circuit determining products of corresponding input feature map and convolution kernel weight values, and an add circuit accumulating the products determined by the multiply circuit in storage. The circuit can perform an average pooling operation by the add circuit accumulating input feature map data values in the storage, a divisor circuit determining a divisor value, and a division circuit dividing the data value accumulated in the storage by the determined divisor value. The circuit can perform a maximum pooling operation by a maximum circuit determining a maximum value of input feature map data values, and storing the determined maximum value in the storage.

9. 发明申请

US20210133542A1 EXECUTING NEURAL NETWORKS ON ELECTRONIC DEVICES 有权
公开(公告)号：US20210133542A1
公开(公告)日：2021-05-06
申请号：US16670140
申请日：2019-10-31
申请人： Arm Limited
发明人： Rune Holm , John Wakefield Brothers, III
IPC分类号： G06N3/063 , G06N3/04 , G06F17/16 , G06F7/544
摘要： When performing a matrix-vector multiply operation for neural network processing, a set of one or more input vectors to be multiplied by a matrix of data values is scanned to identify data positions of the input vector(s) for which the data value is non-zero in at least one of the input vectors. For each of the data positions identified as having a non-zero value in at least one of the input vectors, the set of data values from the matrix of data values for that data position is fetched from memory and the matrix-vector multiply operation is performed using the data values for the input vectors for the data positions identified as being non-zero and the fetched set(s) of data values from the matrix of data values for those data position(s).

10. 发明授权

US12032506B2 Multi-processor arrangement with point of serialization for broadcast communications 有权
公开(公告)号：US12032506B2
公开(公告)日：2024-07-09
申请号：US17709280
申请日：2022-03-30
申请人： Arm Limited
发明人： Erik Persson , Graeme Leslie Ingram , Rune Holm , John Wakefield Brothers, III
IPC分类号： H04L49/101 , G06F13/42 , G06N5/04
CPC分类号： G06F13/42 , G06N5/04
摘要： The present disclosure relates generally to multi-processor arrangements and, more particularly, to a point of serialization for broadcast communications within multi-processor arrangements.

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