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1. 发明授权

US11580402B2 System and method for compressing activation data 有权
公开(公告)号：US11580402B2
公开(公告)日：2023-02-14
申请号：US16871785
申请日：2020-05-11
申请人： Arm Limited
发明人： Erik Persson , Sven Ola Johannes Hugosson
IPC分类号： G06N3/08 , G06N3/082 , G06N3/084 , H03M7/30 , H03M7/40 , G06N20/00
摘要： A method for adapting a trained neural network is provided. Input data is input to the trained neural network and a plurality of filters are applied to generate a plurality of channels of activation data. Differences between corresponding activation values in the plurality of channels of activation data are calculated and an order of the plurality of channels is determined based on the calculated differences. The neural network is adapted so that it will output channels of activation data in the determined order. The ordering of the channels of activation data is subsequently used to compress activation data values by taking advantage of a correlation between activation data values in adjacent channels.

2. 发明申请

US20170061577A1 METHOD OF AND APPARATUS FOR SCALING DATA ARRAYS 审中-公开
标题翻译：用于扩展数据阵列的方法和装置
公开(公告)号：US20170061577A1
公开(公告)日：2017-03-02
申请号：US15238873
申请日：2016-08-17
申请人： ARM Limited
发明人： Michal Bogusz , Erik Persson
IPC分类号： G06T3/40
CPC分类号： G06T3/40 , G06T1/60
摘要： A scaling apparatus for scaling data arrays, such as images, comprises first horizontal scaling stage circuitry operable to scale a data array input to the scaling apparatus in the horizontal direction, one or more line memories for storing horizontal lines for a data array, wherein the or each line memory is for storing a horizontal line of data for the data array, vertical scaling stage circuitry operable to read data stored in the one or more line memories and to scale the read data in the vertical direction, and second horizontal scaling stage circuitry operable to scale a data array in the horizontal direction.
摘要翻译：用于缩放数据阵列（诸如图像）的缩放装置包括可操作以在水平方向上缩放输入到缩放设备的数据阵列的第一水平缩放级电路，用于存储用于数据阵列的水平线的一个或多个行存储器，其中，或者每行存储器用于存储用于数据阵列的水平线数据，垂直缩放级电路可操作以读取存储在一个或多个行存储器中的数据，并在垂直方向上缩放读数据;以及第二水平缩放级电路可操作以在水平方向上缩放数据阵列。

3. 发明授权

US12001369B2 Broadcast regions for multi-processor arrangement 有权
公开(公告)号：US12001369B2
公开(公告)日：2024-06-04
申请号：US17709293
申请日：2022-03-30
申请人： Arm Limited
发明人： Erik Persson , Graeme Leslie Ingram , Rune Holm , John Wakefield Brothers, III
IPC分类号： G06F13/42 , G06N5/04
CPC分类号： G06F13/42 , G06N5/04
摘要： The present disclosure relates generally to multi-processor arrangements and, more particularly, to broadcast regions for multi-processor arrangements.

4. 发明公开

US20230315670A1 BROADCAST REGIONS FOR MULTI-PROCESSOR ARRANGEMENT 审中-公开
公开(公告)号：US20230315670A1
公开(公告)日：2023-10-05
申请号：US17709293
申请日：2022-03-30
申请人： Arm Limited
发明人： Erik Persson , Graeme Leslie Ingram , Rune Holm , John Wakefield Brothers, III
IPC分类号： G06F13/42 , G06N5/04
CPC分类号： G06F13/42 , G06N5/04
摘要： The present disclosure relates generally to multi-processor arrangements and, more particularly, to broadcast regions for multi-processor arrangements.

5. 发明授权

US10938411B1 Compression and/or decompression of activation data 有权
公开(公告)号：US10938411B1
公开(公告)日：2021-03-02
申请号：US16829879
申请日：2020-03-25
申请人： Arm Limited
发明人： Derek David Whiteman , Erik Persson , Tomas Fredrik Edsö
IPC分类号： H03M7/40 , H03M7/30 , G06N3/02
摘要： A method for compressing activation data of a neural network to be written to a storage is provided. The activation data is formed into a plurality of groups and a state indicator indicates whether there are any data elements within each group that have a non-zero value. A second state indicator indicates, for groups having a non-zero value, whether sub-groups within the group contain a data element having a non-zero value. A sub-group state indicator indicates, for each sub-group having a non-zero value, which data elements within that sub-group have a non-zero value. Non-zero values of data elements in the activation data are encoded and a compressed data set is formed comprising the first state indicators, any second state indicators, any sub-group state indicators and the encoded non-zero values.

6. 发明申请

US20190196745A1 DATA PROCESSING SYSTEMS 审中-公开
公开(公告)号：US20190196745A1
公开(公告)日：2019-06-27
申请号：US16226584
申请日：2018-12-19
申请人： Arm Limited
发明人： Erik Persson , Stefan Johannes Frid , Philip Gregory Hall , Dominic Hugo Symes , Sven Ola Johannes Hugosson , Robert Norberg
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/0673
摘要： A producer processing unit of a data processing system that is producing a stream of data for use by one or more consumer processing units of the data processing system maintains a record that is accessible to the consumer processing units of a position in the data stream for which it has written data to memory. The consumer processing units then control their reading of the data stream from the memory in accordance with the write position record maintained by the producer processing unit.

7. 发明授权

US09213650B2 Memory management unit 有权
标题翻译：内存管理单元
公开(公告)号：US09213650B2
公开(公告)日：2015-12-15
申请号：US14560464
申请日：2014-12-04
申请人： ARM Limited
发明人： Erik Persson , Ola Hugosson , Andreas Bjorklund
IPC分类号： G06F12/10 , G06F12/12
CPC分类号： G06F12/1018 , G06F12/1027 , G06F12/122
摘要： A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided.
摘要翻译：提供了一种数据处理装置，包括被配置为发布包括虚拟地址的存储器访问请求的多个主设备。存储器管理单元被配置为接收存储器访问请求并将包括在存储器访问请求中的虚拟地址从请求主设备转换成指示存储器中的存储位置的物理地址。存储器管理单元具有内部存储单元，其具有多个条目，其中存储对应的虚拟地址部分和物理地址部分的指示。存储器管理单元被配置为根据虚拟地址和请求主设备的标识符来选择内部存储单元的条目。因此避免了主设备在使用内部存储单元时的冲突。

8. 发明授权

US10148963B2 Methods of and apparatus for encoding data arrays 有权
公开(公告)号：US10148963B2
公开(公告)日：2018-12-04
申请号：US15274044
申请日：2016-09-23
申请人： ARM Limited
发明人： Erik Persson , Fredrik Peter Stolt
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04 , H04N19/137 , H04N19/105 , H04N19/513 , H04N19/86 , H04N19/59 , H04N19/172 , H04N19/176 , H04N19/182
摘要： To perform motion estimation for a video frame block to be encoded, a difference measure is determined for each of a plurality of reference frame block positions at a first, coarser resolution. The determined difference measures are then used estimate difference measures for reference frame blocks at positions at a second resolution that is finer than the first resolution. The estimated second, finer position resolution difference measures are then used to select a set of reference frame block positions for which to determine “full” difference measures. The determined “full” difference measures for each of the selected reference frame block positions are then used to select the reference frame block position to use when encoding the frame block and a motion vector corresponding to that reference frame block position is associated with and encoded for the frame block being encoded.

9. 发明申请

US20180091818A1 METHODS OF AND APPARATUS FOR ENCODING DATA ARRAYS 审中-公开
公开(公告)号：US20180091818A1
公开(公告)日：2018-03-29
申请号：US15274044
申请日：2016-09-23
申请人： ARM Limited
发明人： Erik Persson , Fredrik Peter Stolt
IPC分类号： H04N19/137 , H04N19/105 , H04N19/513 , H04N19/86 , H04N19/59
CPC分类号： H04N19/523 , H04N19/53
摘要： To perform motion estimation for a video frame block to be encoded, a difference measure is determined for each of a plurality of reference frame block positions at a first, coarser resolution. The determined difference measures are then used estimate difference measures for reference frame blocks at positions at a second resolution that is finer than the first resolution. The estimated second, finer position resolution difference measures are then used to select a set of reference frame block positions for which to determine “full” difference measures. The determined “full” difference measures for each of the selected reference frame block positions are then used to select the reference frame block position to use when encoding the frame block and a motion vector corresponding to that reference frame block position is associated with and encoded for the frame block being encoded.

10. 发明申请

US20160100172A1 DATA PROCESSING SYSTEMS 审中-公开
标题翻译：数据处理系统
公开(公告)号：US20160100172A1
公开(公告)日：2016-04-07
申请号：US14873037
申请日：2015-10-01
申请人： ARM Limited
发明人： Ola Hugosson , Tomas Edsö , Erik Persson
IPC分类号： H04N19/172 , H04N19/142 , H04N19/176
CPC分类号： H04N19/127 , H04N19/137 , H04N19/142 , H04N19/174 , H04N19/46
摘要： A data processing system comprises a video processor (3). The data processing system is configured to, when a new frame (10) is to be encoded by the video processor (3), determine for a sub-region of a set of plural sub-regions that the new frame (10) is divided into, whether the sub-region has changed from a previous frame (11), and to control the encoding operation for the new frame (10) on the basis of the determination, e.g. to avoid performing motion estimation.
摘要翻译：数据处理系统包括视频处理器（3）。数据处理系统被配置为当新的帧（10）将由视频处理器（3）编码时，确定新帧（10）被划分的多个子区域的集合的子区域进入，子区域是否已经从先前帧（11）改变，并且基于该确定来控制新帧（10）的编码操作，例如以避免执行运动估计。

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