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    • 8. 发明授权
    • Data transmission and reception system, data transmitter and data receiver
    • 数据收发系统,数据发射机和数据接收机
    • US06959011B2
    • 2005-10-25
    • US09734618
    • 2000-12-13
    • Koichi TakizawaKazuo KuboHiroshi Ichibangase
    • Koichi TakizawaKazuo KuboHiroshi Ichibangase
    • H04J3/00H04J3/06H04J3/16H04L7/08
    • H04J3/1611H04J3/0608
    • The data transmission and reception system comprises a data transmitter and a data receiver. The data transmitter generates and transmits a high-speed serial signal through a transmission path and the data receiver receives the serial signal. The data transmitter, when forming the frame for every tributary signal, inserts into the frame a frame bit indicating a boundary of the frame and, after having formed the frame, performs only a bit synchronization with respect to every tributary signal. On the other hand, the data receiver, for a respective tributary signal, stores a data indicated by the tributary signal and, in a timing based on a detection of the frame bit of the tributary signal and a reference frame pulse commonly issued between tributary signals, outputs the stored data to thereby perform the tributary synchronization.
    • 数据发送和接收系统包括数据发送器和数据接收器。 数据发送器通过传输路径产生并发送高速串行信号,数据接收器接收串行信号。 数据发送器在为每个支路信号形成帧时,将表示帧的边界的帧比特插入到帧中,并且在形成帧之后,仅对每个支路信号执行比特同步。 另一方面,对于相应的支路信号,数据接收机存储由辅助信号指示的数据,并且在基于支路信号的帧位的检测的定时以及通常在支路信号之间发出的参考帧脉冲 ,输出所存储的数据,从而执行支路同步。
    • 9. 发明授权
    • Optical transmission system, fec multiplexer, fec multiplexer/separator, and error correction method
    • 光传输系统,fec多路复用器,fec多路复用器/分离器和纠错方法
    • US07043162B2
    • 2006-05-09
    • US10031235
    • 2001-05-16
    • Kazuo KuboHideo YoshidaHiroshi Ichibangase
    • Kazuo KuboHideo YoshidaHiroshi Ichibangase
    • H04B10/00
    • H03M13/29H03M13/03H03M13/15H03M13/1515H03M13/2909H04L1/0041H04L1/005H04L1/0057H04L1/0066H04L1/0071
    • An FEC multiplexing circuit (2) has a configuration in which a first memory circuit (15) is arranged on the input stage of a first RS encoding circuit (16), a second memory circuit (17) is arranged on the input stage of a second RS encoding circuit (18), error correction encoding is performed by a combination of different data having two directions, and thereafter, error correction codes are multiplexed to generate an FEC frame. On the other hand, an FEC demultiplexing circuit (6) has a configuration in which a third memory circuit (42) is arranged on the output stage of a first RS decoding circuit (41), a fourth memory circuit (44) is arranged on the output stage of a second RS decoding circuit (43), error correction is performed by a combination of different data having two directions, and, thereafter, parallel data read from the fourth memory circuit (44) are multiplexed to reproduce original information data.
    • FEC复用电路(2)具有第一存储器电路(15)布置在第一RS编码电路(16)的输入级上的配置,第二存储器电路(17)布置在输入级 第二RS编码电路(18),通过具有两个方向的不同数据的组合来执行纠错编码,然后对纠错码进行多路复用以产生FEC帧。 另一方面,FEC解复用电路(6)具有第三存储电路(42)配置在第一RS解码电路(41)的输出级上的结构,第四存储电路(44)配置在 通过具有两个方向的不同数据的组合来执行第二RS解码电路(43)的输出级,然后对从第四存储器电路(44)读取的并行数据进行多路复用以再现原始信息数据。