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1. 发明授权

US06038168A Hot-electron programmable latch for integrated circuit fuse applications and method of programming therefor 失效
标题翻译：用于集成电路保险丝应用的热电子可编程锁存器及其编程方法
公开(公告)号：US06038168A
公开(公告)日：2000-03-14
申请号：US105339
申请日：1998-06-26
申请人： Archibald J. Allen , Jerome B. Lasky , John J. Pekarik , Jed H. Rankin , Francis R. White
发明人： Archibald J. Allen , Jerome B. Lasky , John J. Pekarik , Jed H. Rankin , Francis R. White
IPC分类号： G11C17/16 , G11C17/18 , G11C7/00
CPC分类号： G11C17/18 , G11C17/16
摘要： A method and apparatus for conditioning an integrated circuit to always enter a desired operating state when actuated by permanently altering at least one component device. An integrated circuit is provided with at least one component transistor wherein a constant high voltage is applied only once to the drain electrode of the transistor for one predetermined period of time while concurrently a constant voltage lower than the high voltage is applied only once to the gate electrode of the transistor, thus causing a permanent channel hot-electron alteration of a gate oxide of the transistor. The integrated circuit may include a plurality of programmable circuits, each capable of assuming a plurality of readable data states when powered up, and each including a plurality of programmable devices for permanently biasing its corresponding programmable circuit to assume one of the readable states upon subsequent power ups.
摘要翻译：一种用于调节集成电路以在通过永久地改变至少一个组件装置致动时始终进入期望操作状态的方法和装置。集成电路设置有至少一个元件晶体管，其中恒定的高电压仅施加一次到晶体管的漏极一个预定时间段，同时将低于高电压的恒定电压仅施加一次到栅极电极，从而导致晶体管的栅极氧化物的永久性通道热电子改变。集成电路可以包括多个可编程电路，每个可编程电路能够在通电时呈现多个可读数据状态，并且每个可编程电路包括多个可编程器件，用于永久地偏置其相应的可编程电路，以在后续电源中呈现可读状态之一 UPS。

2. 发明授权

US6090673A Device contact structure and method for fabricating same 失效
标题翻译：器件接触结构及其制造方法
公开(公告)号：US6090673A
公开(公告)日：2000-07-18
申请号：US175304
申请日：1998-10-20
申请人： Archibald J. Allen , Toshiharu Furukawa , Edward F. O'Neil , Mark C. Hakey , Roger A. Verhelst , David V. Horak
发明人： Archibald J. Allen , Toshiharu Furukawa , Edward F. O'Neil , Mark C. Hakey , Roger A. Verhelst , David V. Horak
IPC分类号： H01L21/336 , H01L21/768 , H01L27/11 , H01L21/3205
CPC分类号： H01L21/76895 , H01L27/1104
摘要： The present invention overcomes the difficulties found in the background art by providing a direct low resistive contact between devices on a semiconductor chip without excessive current leakage. Current leakage is prevented in the preferred design by using silicon on insulator (SOI) construction for the chip. By constructing the direct contact over an insulator, such as silicon dioxide, current leakage is minimized. The preferred embodiment uses silicide to connect a polysilicon gate to a doped region of the substrate. An alternative embodiment of the present invention provides for the use of conductive studs to electrically connect devices. An increased density of approximately twenty percent may be realized using the present invention.
摘要翻译：本发明通过在半导体芯片上的器件之间提供直接的低电阻接触而克服了背景技术中的困难，而没有过多的电流泄漏。通过使用芯片上的绝缘体硅（SOI）结构，在优选设计中防止电流泄漏。通过在诸如二氧化硅之类的绝缘体上构建直接接触，电流泄漏最小化。优选实施例使用硅化物将多晶硅栅极连接到衬底的掺杂区域。本发明的替代实施例提供了使用导电柱来电连接装置。使用本发明可以实现大约20％的增加的密度。

3. 发明授权

US06429469B1 Optical Proximity Correction Structures Having Decoupling Capacitors 失效
标题翻译：具有去耦电容器的光学接近校正结构
公开(公告)号：US06429469B1
公开(公告)日：2002-08-06
申请号：US09705031
申请日：2000-11-02
申请人： Archibald J. Allen , Orest Bula , John M. Cohn , Daniel Cole , Edward W. Conrad , William C. Leipold
发明人： Archibald J. Allen , Orest Bula , John M. Cohn , Daniel Cole , Edward W. Conrad , William C. Leipold
IPC分类号： H01L2710
CPC分类号： H01L27/0629
摘要： A structure for a semiconductor chip which includes a first region having first cells for storing and processing data, and a second region outside the first region having OPC structures, wherein the OPC structures comprise decoupling capacitors. The line widths of the active gates of first cells are the same size or similar in size as the OPC structures. The OPC structures reduce proximity effects of active devices in the first cells, and comprise N-type FETs and P-type FETs, that are located in the second region. The OPC structures may have a width greater than the first cells. The second region can be multiple OPC structures, whereby the second region comprises multiple decoupling capacitors. The active devices in the first cells are separated by a first distance and the OPC structures are separated from the active devices by the first distance.
摘要翻译：一种用于半导体芯片的结构，其包括具有用于存储和处理数据的第一单元的第一区域，以及具有OPC结构的第一区域之外的第二区域，其中OPC结构包括去耦电容器。第一单元的有源栅极的线宽与OPC结构尺寸相同或相似。 OPC结构减少了第一单元中的有源器件的邻近效应，并且包括位于第二区域中的N型FET和P型FET。 OPC结构可以具有大于第一单元的宽度。第二区域可以是多个OPC结构，由此第二区域包括多个去耦电容器。第一单元中的有源器件被隔开第一距离，并且OPC结构与有源器件分开第一距离。

4. 发明授权

US06738954B1 Method for prediction random defect yields of integrated circuits with accuracy and computation time controls 有权
标题翻译：用于精确计算时间控制的集成电路预测随机缺陷产量的方法
公开(公告)号：US06738954B1
公开(公告)日：2004-05-18
申请号：US09636478
申请日：2000-08-10
申请人： Archibald J. Allen , Wilm E. Donath , Alan D. Dziedzic , Mark A. Lavin , Daniel N. Maynard , Dennis M. Newns , Gustavo E. Tellez
发明人： Archibald J. Allen , Wilm E. Donath , Alan D. Dziedzic , Mark A. Lavin , Daniel N. Maynard , Dennis M. Newns , Gustavo E. Tellez
IPC分类号： G06F1750
CPC分类号： H01L22/20 , G01R31/31705
摘要： A method of computing a manufacturing yield of an integrated circuit having device shapes includes sub-dividing the integrated circuit into failure mechanism subdivisions (each of the failure mechanism subdivisions includes one or more failure mechanism and each of the failure mechanisms includes one or more defect mechanisms), partitioning the failure mechanism subdivisions by area into partitions, pre-processing the device shapes in each partition, computing an initial average number of faults for each of the failure mechanisms and for each partition by numerical integration of an average probability of failure of each failure mechanism, (the numerical integration produces a list of defect sizes for each defect mechanism, and the computing of the initial average includes setting a maximum integration error limit, a maximum sample size for a population of each defect size, and a maximum number of allowable faults for each failure mechansim), and computing a final average number of faults for the integrated circuit by iterativelly reducing a statistical error of the initial average number of faults for each of the failure mechanisms until the statistical error is below an error limit.
摘要翻译：一种计算具有装置形状的集成电路的制造成品率的方法包括将集成电路分为故障机构细分（每个故障机构细分包括一个或多个故障机制，并且每个故障机制包括一个或多个缺陷机构），将故障机制细分为每个区域的分区，预处理每个分区中的设备形状，通过对每个分区的每个故障机制和每个分区的平均故障概率的数值积分计算每个故障机制的初始平均故障数故障机制（数值积分产生每个缺陷机制的缺陷尺寸列表，初始平均值的计算包括设置最大积分误差极限，每个缺陷尺寸的总体最大样本量，每个故障的可允许故障mechansim），并计算最终的平均数fau 通过迭代地减少每个故障机制的初始平均故障数量的统计误差，直到统计误差低于误差极限为止，用于集成电路。

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