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1. 发明授权

US09182811B2 Interfacing dynamic hardware power managed blocks and software power managed blocks 有权
标题翻译：接口动态硬件电源管理块和软件电源管理块
公开(公告)号：US09182811B2
公开(公告)日：2015-11-10
申请号：US13719535
申请日：2012-12-19
申请人： Apple Inc.
发明人： Erik P Machnicki , Gurjeet S Saund , Munetoshi Fukami , Shane J Keil , Chaitanya Kosaraju , Erdem Guleyupoglu , Jason M Kassoff , Kevin C Wong
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3206 , G06F1/3246 , G06F1/329 , G06F1/3293 , Y02D10/24 , Y02D50/20
摘要： A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.
摘要翻译：公开了用于接口动态硬件功率管理块和软件功率管理块的方法和装置。在一个实施例中，集成电路（IC）可以包括多个功率可管理的功能单元。功能单元可以通过硬件，软件或两者进行功率管理。每个功能单元可以通过直接通信链路耦合到至少一个其它功能单元。链路状态机可以监视功能单元之间的每个通信链路，并且可以将链路可用性的指示广播到耦合到链路的功能单元。响应于关闭给定链路的软件请求或耦合到链路的功能单元之一的硬件启动关机，链路状态机可以广播并指示链路不可用。

2. 发明申请

US20140241376A1 Apparatus and Method for Controlling Transaction Flow in Integrated Circuits 有权
标题翻译：用于控制集成电路中事务流的装置和方法
公开(公告)号：US20140241376A1
公开(公告)日：2014-08-28
申请号：US13778482
申请日：2013-02-27
申请人： APPLE INC.
发明人： Deniz Balkan , Gurjeet S Saund , Kevin C Wong , Munetoshi Fukami
IPC分类号： H04L12/56
CPC分类号： H04L47/6275 , H04L47/6205 , H04L47/6295 , H04W28/10
摘要： Various embodiments of a method and apparatus for controlling transaction flow in a communications fabric is disclosed. In one embodiment, an IC includes a communications fabric connecting multiple agents to one another. Each agent may include an interface coupling itself to at least one other agent. Each interface may include multiple queues for storing information corresponding to pending transactions. Also included in each interface is an arbitration unit and control logic. The control logic may determine which transactions are presented to the arbitration unit for arbitration. In one embodiment, the control logic may inhibit certain transactions from being presented to the arbitration unit so that other higher priority transactions may advance. In another embodiment, the control logic may reduce the priority level of some transactions for arbitration purposes to prevent the blocking of other higher priority transactions.
摘要翻译：公开了用于控制通信结构中的事务流的方法和装置的各种实施例。在一个实施例中，IC包括将多个代理彼此连接的通信结构。每个代理可以包括将自身耦合到至少一个其他代理的接口。每个接口可以包括用于存储对应于待处理事务的信息的多个队列。每个接口中还包括一个仲裁单元和控制逻辑。控制逻辑可以确定哪些事务被呈现给仲裁单元进行仲裁。在一个实施例中，控制逻辑可以禁止某些交易被呈现给仲裁单元，使得其他更高优先级的事务可以提前。在另一个实施例中，控制逻辑可以减少用于仲裁目的的一些交易的优先级，以防止阻塞其他更高优先级的事务。

3. 发明申请

US20140173342A1 DEBUG ACCESS MECHANISM FOR DUPLICATE TAG STORAGE 有权
标题翻译：用于重复标签存储的调试访问机制
公开(公告)号：US20140173342A1
公开(公告)日：2014-06-19
申请号：US13713654
申请日：2012-12-13
申请人： APPLE INC.
发明人： Harshavardhan Kaushikkar , Muditha Kanchana , Gurjeet S Saund , Odutola O Ewedemi
IPC分类号： G06F11/273
CPC分类号： G06F11/273 , G06F11/221 , G06F11/2236
摘要： A coherence system includes a storage array that may store duplicate tag information associated with a cache memory of a processor. The system may also include a pipeline unit that includes a number of stages to control accesses to the storage array. The pipeline unit may pass through the pipeline stages, without generating an access to the storage array, an input/output (I/O) request that is received on a fabric. The system may also include a debug engine that may reformat the I/O request from the pipeline unit into a debug request. The debug engine may send the debug request to the pipeline unit via a debug bus. In response to receiving the debug request, the pipeline unit may access the storage array. The debug engine may return to the source of the I/O request via the fabric bus, a result of the access to the storage array.
摘要翻译：相干系统包括可存储与处理器的高速缓冲存储器相关联的重复标签信息的存储阵列。系统还可以包括流水线单元，其包括多个级以控制对存储阵列的访问。流水线单元可以通过流水线阶段，而不产生对存储阵列的访问，即在结构上接收的输入/输出（I / O）请求。该系统还可以包括可以将流水线单元的I / O请求重新格式化为调试请求的调试引擎。调试引擎可以通过调试总线将调试请求发送到流水线单元。响应于接收到调试请求，流水线单元可以访问存储阵列。调试引擎可以通过结构总线返回到I / O请求的源，这是访问存储阵列的结果。

4. 发明授权

US09229894B2 Protocol conversion involving multiple virtual channels 有权
标题翻译：涉及多个虚拟通道的协议转换
公开(公告)号：US09229894B2
公开(公告)日：2016-01-05
申请号：US13859000
申请日：2013-04-09
申请人： Apple Inc.
发明人： Deniz Balkan , Gurjeet S Saund , Joseph P Bratt , Kevin C Wong , Manu Gulati , Rohit K Gupta
IPC分类号： G06F13/42 , G06F3/00 , G06F13/36 , G06F13/38
CPC分类号： G06F13/385
摘要： Embodiments of a bridge circuit and system are disclosed that may allow converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The second bus may include a plurality of virtual channels. The bridge circuit may be configured to receive transactions over the first bus, and convert the transactions to the second communication protocol, and to assign the converted transaction to one of the plurality of virtual channels. The bridge circuit may be further configured store the converted transaction. A plurality of limited throughput signals may be generated by the bridge circuit dependent upon a number of available credits for the plurality of virtual channels.
摘要翻译：公开了桥接电路和系统的实施例，其可以允许将事务从一个通信协议转换到另一个通信协议。桥接电路可以耦合到采用第一通信协议的第一总线，以及采用第二通信协议的第二总线。第二总线可以包括多个虚拟通道。桥接电路可以被配置为通过第一总线接收事务，并将事务转换为第二通信协议，并将转换的事务分配给多个虚拟通道中的一个。可以进一步配置桥接电路来存储转换的事务。取决于多个虚拟信道的可用信用数量，桥电路可以产生多个有限吞吐量信号。

5. 发明授权

US08793411B1 Bridge circuit reorder buffer for transaction modification and translation 有权
标题翻译：桥接电路重排序缓冲器用于事务修改和翻译
公开(公告)号：US08793411B1
公开(公告)日：2014-07-29
申请号：US13785983
申请日：2013-03-05
申请人： Apple Inc.
发明人： Deniz Balkan , Gurjeet S Saund
IPC分类号： G06F13/28
CPC分类号： G06F13/4027 , G06F13/28
摘要： Embodiments of a bridge circuit and system are disclosed that may allow for converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The bridge circuit may be configured to receive transactions over the first bus and store parameters associated with the received transactions. The bridge circuit may be further configured to modify the received transaction, convert the modified transaction to the second communication protocol, and transmit the converted transaction over the second bus.
摘要翻译：公开了桥接电路和系统的实施例，其可以允许将事务从一个通信协议转换到另一个通信协议。桥接电路可以耦合到采用第一通信协议的第一总线，以及采用第二通信协议的第二总线。桥接电路可以被配置为通过第一总线接收事务并存储与所接收的事务相关联的参数。桥接电路还可以被配置为修改接收到的事务，将修改后的事务转换为第二通信协议，并通过第二总线发送转换的事务。

6. 发明授权

US09310783B2 Dynamic clock and power gating with decentralized wake-ups 有权
标题翻译：动态时钟和电源门控与分散唤醒
公开(公告)号：US09310783B2
公开(公告)日：2016-04-12
申请号：US13719517
申请日：2012-12-19
申请人： Apple Inc.
发明人： Erik P Machnicki , Gurjeet S Saund , Munetoshi Fukami , Shane J Keil
IPC分类号： G05B11/01 , G06F1/32
CPC分类号： G05B11/01 , G06F1/3237 , G06F1/3253 , Y02D10/128 , Y02D10/151 , Y02D50/20
摘要： A method and apparatus for dynamic clock and power gating and decentralized wakeups is disclosed. In one embodiment, an integrated circuit (IC) includes power-manageable functional units and a power management unit. Each of the power manageable functional units is configured to convey a request to enter a low power state to the power management unit. The power management unit may respond by causing a requesting functional unit to enter the low power state. Should another functional unit initiate a request to communicate with a functional unit currently in the low power state, it may send a request to that functional unit. The receiving functional unit may respond to the request by exiting the low power state and resuming operation in the active state.
摘要翻译：公开了一种用于动态时钟和电源门控和分散式唤醒的方法和装置。在一个实施例中，集成电路（IC）包括功率可管理的功能单元和电源管理单元。每个功率可管理功能单元被配置为向电力管理单元传送进入低功率状态的请求。功率管理单元可以通过使请求功能单元进入低功率状态来进行响应。如果另一个功能单元发起与当前处于低功率状态的功能单元通信的请求，则它可以向该功能单元发送请求。接收功能单元可以通过退出低功率状态并在活动状态下恢复运行来响应该请求。

7. 发明授权

US09270610B2 Apparatus and method for controlling transaction flow in integrated circuits 有权
标题翻译：集成电路中控制事务流的装置和方法
公开(公告)号：US09270610B2
公开(公告)日：2016-02-23
申请号：US13778482
申请日：2013-02-27
申请人： Apple Inc.
发明人： Deniz Balkan , Gurjeet S Saund , Kevin C Wong , Munetoshi Fukami
IPC分类号： H04L12/865 , H04L12/863 , H04W28/10
CPC分类号： H04L47/6275 , H04L47/6205 , H04L47/6295 , H04W28/10
摘要： Various embodiments of a method and apparatus for controlling transaction flow in a communications fabric is disclosed. In one embodiment, an IC includes a communications fabric connecting multiple agents to one another. Each agent may include an interface coupling itself to at least one other agent. Each interface may include multiple queues for storing information corresponding to pending transactions. Also included in each interface is an arbitration unit and control logic. The control logic may determine which transactions are presented to the arbitration unit for arbitration. In one embodiment, the control logic may inhibit certain transactions from being presented to the arbitration unit so that other higher priority transactions may advance. In another embodiment, the control logic may reduce the priority level of some transactions for arbitration purposes to prevent the blocking of other higher priority transactions.
摘要翻译：公开了用于控制通信结构中的事务流的方法和装置的各种实施例。在一个实施例中，IC包括将多个代理彼此连接的通信结构。每个代理可以包括将自身耦合到至少一个其他代理的接口。每个接口可以包括用于存储对应于待处理事务的信息的多个队列。每个接口中还包括一个仲裁单元和控制逻辑。控制逻辑可以确定哪些事务被呈现给仲裁单元进行仲裁。在一个实施例中，控制逻辑可以禁止某些交易被呈现给仲裁单元，使得其他更高优先级的事务可以提前。在另一个实施例中，控制逻辑可以减少用于仲裁目的的一些交易的优先级，以防止阻塞其他更高优先级的事务。

8. 发明授权

US09152210B2 Method and apparatus for determining tunable parameters to use in power and performance management 有权
标题翻译：用于确定在功率和性能管理中使用的可调谐参数的方法和装置
公开(公告)号：US09152210B2
公开(公告)日：2015-10-06
申请号：US13767897
申请日：2013-02-15
申请人： Apple Inc.
发明人： Erik P Machnicki , Brian P Lilly , Gurjeet S Saund , Sukalpa Biswas
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： Various method and apparatus embodiments for selecting tunable operating parameters in an integrated circuit (IC) are disclosed. In one embodiment, an IC includes a number of various functional blocks each having a local management circuit. The IC also includes a global management unit coupled to each of the functional blocks having a local management circuit. The management unit is configured to determine the operational state of the IC based on the respective operating states of each of the functional blocks. Responsive to determining the operational state of the IC, the management unit may provide indications of the same to the local management circuit of each of the functional blocks. The local management circuit for each of the functional blocks may select one or more tunable parameters based on the operational state determined by the management unit.
摘要翻译：公开了用于在集成电路（IC）中选择可调工作参数的各种方法和装置实施例。在一个实施例中，IC包括多个各自具有本地管理电路的功能块。 IC还包括耦合到具有本地管理电路的每个功能块的全局管理单元。管理单元被配置为基于每个功能块的各自的操作状态来确定IC的操作状态。响应于确定IC的操作状态，管理单元可以向每个功能块的本地管理电路提供相同的指示。每个功能块的本地管理电路可以基于由管理单元确定的操作状态来选择一个或多个可调参数。

9. 发明授权

US09021306B2 Debug access mechanism for duplicate tag storage 有权
标题翻译：重复标签存储的调试访问机制
公开(公告)号：US09021306B2
公开(公告)日：2015-04-28
申请号：US13713654
申请日：2012-12-13
申请人： Apple Inc.
发明人： Harshavardhan Kaushikkar , Muditha Kanchana , Gurjeet S Saund , Odutola O Ewedemi
IPC分类号： G06F11/00 , G06F11/273 , G06F11/22
CPC分类号： G06F11/273 , G06F11/221 , G06F11/2236
摘要： A coherence system includes a storage array that may store duplicate tag information associated with a cache memory of a processor. The system may also include a pipeline unit that includes a number of stages to control accesses to the storage array. The pipeline unit may pass through the pipeline stages, without generating an access to the storage array, an input/output (I/O) request that is received on a fabric. The system may also include a debug engine that may reformat the I/O request from the pipeline unit into a debug request. The debug engine may send the debug request to the pipeline unit via a debug bus. In response to receiving the debug request, the pipeline unit may access the storage array. The debug engine may return to the source of the I/O request via the fabric bus, a result of the access to the storage array.
摘要翻译：相干系统包括可存储与处理器的高速缓冲存储器相关联的重复标签信息的存储阵列。系统还可以包括流水线单元，其包括多个级以控制对存储阵列的访问。流水线单元可以通过流水线阶段，而不产生对存储阵列的访问，即在结构上接收的输入/输出（I / O）请求。该系统还可以包括可以将流水线单元的I / O请求重新格式化为调试请求的调试引擎。调试引擎可以通过调试总线将调试请求发送到流水线单元。响应于接收到调试请求，流水线单元可以访问存储阵列。调试引擎可以通过结构总线返回到I / O请求的源，这是访问存储阵列的结果。

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