专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07554133B1 Pad current splitting 有权
标题翻译：垫电流分流
公开(公告)号：US07554133B1
公开(公告)日：2009-06-30
申请号：US12119575
申请日：2008-05-13
申请人： Anwar Ali , Nenad Miladinovic , Kalyan Doddapaneni
发明人： Anwar Ali , Nenad Miladinovic , Kalyan Doddapaneni
IPC分类号： H01L27/10 , H01L29/73 , H01L23/52
CPC分类号： H01L23/5286 , H01L24/05 , H01L24/06 , H01L2224/05554 , H01L2924/01014 , H01L2924/01023 , H01L2924/01032 , H01L2924/01033 , H01L2924/14
摘要： An integrated circuit with a monolithic semiconducting substrate formed in a chip, where the chip has a peripheral edge, a backside, and an opposing top on which circuitry is formed. A first ring of bonding pads is formed along at least a portion of the peripheral edge. At least one of the bonding pads is configured as a power pad, and at least one of the bonding pads is configured as a ground pad. An intermediate power bus is disposed interior to the first ring of bonding pads on the chip, and forms no direct electrical connections to any core devices. An intermediate ground bus is also disposed interior to the first ring of bonding pads on the chip, and forms no direct electrical connections to any core devices. A power pad wire forms an exclusive electrical connection between the power pad and the intermediate power bus. A ground pad wire forms an exclusive electrical connection between the ground pad and the intermediate ground bus. A power strap forms an electrical connection between the intermediate power bus and a power mesh. A ground strap forms an electrical connection between the intermediate ground bus and a ground mesh.
摘要翻译：一种具有形成在芯片中的单片半导体衬底的集成电路，其中芯片具有外围边缘，背面和形成有电路的相对顶部。沿周边边缘的至少一部分形成第一接合焊盘。至少一个接合焊盘被配置为电源焊盘，并且至少一个焊盘被配置为接地焊盘。中间电源总线设置在芯片上的第一环焊盘的内部，并且不形成与任何核心器件的直接电连接。中间接地母线也设置在芯片上的第一环焊盘的内部，并且不形成与任何核心器件的直接电连接。电源焊盘线在电源板和中间电源总线之间形成专用电气连接。接地焊盘线在接地焊盘和中间接地总线之间形成专用电气连接。电源带形成中间电源总线和电源网之间的电连接。接地线在中间接地母线和地面网之间形成电气连接。

2. 发明授权

US09294132B1 Dual-stage data decoding for non-volatile memories 有权
标题翻译：用于非易失性存储器的双级数据解码
公开(公告)号：US09294132B1
公开(公告)日：2016-03-22
申请号：US13672047
申请日：2012-11-08
申请人： Borja Peleato-Inarrea , Andrei Vityaev , Nenad Miladinovic
发明人： Borja Peleato-Inarrea , Andrei Vityaev , Nenad Miladinovic
IPC分类号： H03M13/29 , G11B20/18 , H03M13/39 , G06F11/10 , H03M13/27
CPC分类号： H03M13/29 , G06F11/1048 , G06F11/1068 , G11B20/1833 , G11B2020/1846 , G11B2020/185 , H03M13/1108 , H03M13/1117 , H03M13/27 , H03M13/2948 , H03M13/3707 , H03M13/3927 , H03M13/6325
摘要： A method and system for decoding information read from a non-volatile memory uses a two stage decoding algorithm, where the first stage is a high-speed, low precision decoder and the second stage is a low-speed, high precision decoder. Most of the time only the first stage of the decoder is used, which lowers the average power consumption of the decoding process.
摘要翻译：用于解码从非易失性存储器读取的信息的方法和系统使用两级解码算法，其中第一级是高速，低精度解码器，第二级是低速，高精度解码器。大多数时候只使用解码器的第一级，这降低了解码过程的平均功耗。

3. 发明授权

US08856616B1 Two dimensional encoding for non-volatile memory blocks 有权
标题翻译：用于非易失性存储器块的二维编码
公开(公告)号：US08856616B1
公开(公告)日：2014-10-07
申请号：US13556088
申请日：2012-07-23
申请人： Borja Manuel Peleato-Inarrea , Andrei Eugenievich Vityaev , Nenad Miladinovic
发明人： Borja Manuel Peleato-Inarrea , Andrei Eugenievich Vityaev , Nenad Miladinovic
IPC分类号： G11C29/00
CPC分类号： G06F11/1012 , G11C2029/0411
摘要： Method for encoding information in a flash memory block which combines an independent encoding of each page with a block-level code across multiple pages. The method includes two independent error correction codes, one in horizontal direction and one in vertical direction, with horizontal direction error correction decoding; and vertical direction erasure correction decoding.
摘要翻译：用于对闪存块中的信息进行编码的方法，其将每个页面的独立编码与跨多个页面的块级代码组合。该方法包括两个独立的纠错码，一个在水平方向和一个在垂直方向，水平方向纠错解码; 和垂直方向消失校正解码。

4. 发明授权

US08634250B2 Methods and apparatus for programming multiple program values per signal level in flash memories 有权
标题翻译：闪存中每个信号电平编程多个程序值的方法和装置
公开(公告)号：US08634250B2
公开(公告)日：2014-01-21
申请号：US13001295
申请日：2009-07-21
申请人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Johnson Yen
发明人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Johnson Yen
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/3454 , G11C2211/5621
摘要： Methods and apparatus are provided for programming multiple program values per signal level in flash memories. A flash memory device having a plurality of program values is programmed by programming the flash memory device for a given signal level, wherein the programming step comprises a programming phase and a plurality of verify phases. In another variation, a flash memory device having a plurality of program values is programmed, and the programming step comprises a programming phase and a plurality of verify phases, wherein at least one signal level comprises a plurality of the program values. The signal levels or the program values (or both) can be represented using one or more of a voltage, a current and a resistance.
摘要翻译：提供了用于在闪速存储器中编程每个信号电平的多个程序值的方法和装置。具有多个编程值的闪速存储器件通过针对给定的信号电平对闪速存储器件进行编程来编程，其中编程步骤包括编程阶段和多个验证阶段。在另一个实施例中，编程具有多个编程值的闪速存储器件，并且编程步骤包括编程阶段和多个验证阶段，其中至少一个信号电平包括多个程序值。可以使用电压，电流和电阻中的一个或多个来表示信号电平或程序值（或两者）。

5. 发明授权

US08526230B2 Methods and apparatus for write-side intercell interference mitigation in flash memories 失效
标题翻译： Flash存储器中写入侧小区间干扰减轻的方法和装置
公开(公告)号：US08526230B2
公开(公告)日：2013-09-03
申请号：US13001286
申请日：2009-06-30
申请人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Johnson Yen
发明人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Johnson Yen
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G06F11/1072 , G11C5/00 , G11C7/02 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3418
摘要： Methods and apparatus are provided for write-side intercell interference mitigation in flash memories. A flash memory device is written by obtaining program data to be written to at least one target cell in the flash memory; obtaining one or more bits of program data for at least one aggressor cell to be programmed later than the target cell: and precompensating for intercell interference for the target cell by generating precompensated program values. The aggressor cells comprise one or more cells adjacent to the target cell, such as adjacent cells in a same wordline as the target cell and/or cells in an upper or lower adjacent wordline to the target cell. The precompensated program values for the target cell are optionally provided to the flash memory.
摘要翻译：提供了用于闪存中的写侧小区间干扰减轻的方法和装置。通过获得写入到闪速存储器中的至少一个目标单元的程序数据来写入闪速存储器件; 为至少一个侵略者单元获得待编程的比目标小区晚的一个或多个程序数据位;并且通过产生预补偿的程序值来预补偿目标小区的小区间干扰。侵略者细胞包括与靶细胞相邻的一个或多个细胞，例如与靶细胞相同的字线中的相邻细胞和/或与靶细胞的上或下相邻字线中的细胞。目标单元的预补偿程序值可选地提供给闪存。

6. 发明申请

US20130007551A1 Stochastic Stream Decoding of Binary LDPC Codes 有权
标题翻译：二进制LDPC码的随机流解码
公开(公告)号：US20130007551A1
公开(公告)日：2013-01-03
申请号：US13174537
申请日：2011-06-30
申请人： Anantha Raman Krishnan , Nenad Miladinovic , Yang Han , Shaohua Yang
发明人： Anantha Raman Krishnan , Nenad Miladinovic , Yang Han , Shaohua Yang
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1117 , H03M13/6577
摘要： Various embodiments of the present invention provide systems and methods for stochastic stream decoding of binary LDPC codes. For example, a data decoder circuit is discussed that includes a number of variable nodes and check nodes, with serial connections between the variable nodes and the check nodes. The variable nodes are each operable to perform a real-valued computation of a variable node to check node message for each neighboring check node. The check nodes are operable to perform a real-valued computation of a check node to variable node message for each neighboring variable node. The messages are passed iteratively between the variable nodes and the check nodes.
摘要翻译：本发明的各种实施例提供了用于二进制LDPC码的随机流解码的系统和方法。例如，讨论了包括多个可变节点和校验节点的数据解码器电路，其中变量节点和校验节点之间具有串行连接。变量节点各自可操作以执行变量节点的实值计算，以检查每个相邻校验节点的节点消息。检查节点可操作用于对每个相邻变量节点执行校验节点对可变节点消息的实值计算。消息在变量节点和校验节点之间迭代地传递。

7. 发明申请

US20120207201A1 Systems and Methods for Data Detection Using Distance Based Tuning 有权
标题翻译：使用基于距离的调整进行数据检测的系统和方法
公开(公告)号：US20120207201A1
公开(公告)日：2012-08-16
申请号：US13310028
申请日：2011-12-02
申请人： Haitao Xia , Weijun Tan , Nenad Miladinovic , Shaohua Yang
发明人： Haitao Xia , Weijun Tan , Nenad Miladinovic , Shaohua Yang
IPC分类号： H04L27/01
CPC分类号： H04L25/03254 , H04L25/0305
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes an equalizer circuit and a data detection circuit. The equalizer circuit is operable to filter a series of samples based at least in part on a filter coefficient and to provide a corresponding series of filtered samples. The data detection circuit includes: a core data detector circuit and a coefficient determination circuit. The core data detector circuit is operable to perform a data detection process on the series of filtered samples and to provide a most likely path and a next most likely path. The coefficient determination circuit operable to update the filter coefficient based at least in part on the most likely path and the next most likely path.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，公开了包括均衡器电路和数据检测电路的数据处理电路。均衡器电路可操作以至少部分地基于滤波器系数对一系列样本进行滤波，并提供相应的一系列滤波样本。数据检测电路包括：核心数据检测器电路和系数确定电路。核心数据检测器电路可操作以对一系列经滤波的样本执行数据检测处理，并提供最可能的路径和下一个最可能的路径。系数确定电路可操作以至少部分地基于最可能的路径和下一个最可能的路径来更新滤波器系数。

8. 发明授权

US09160369B1 Method for iterative error correction with designed error floor performance 有权
标题翻译：具有设计误差平台性能的迭代纠错方法
公开(公告)号：US09160369B1
公开(公告)日：2015-10-13
申请号：US14192041
申请日：2014-02-27
申请人： Nenad Miladinovic
发明人： Nenad Miladinovic
IPC分类号： H04L1/00 , H03M13/11 , H03M13/29
CPC分类号： H03M13/2942 , H03M13/1102 , H03M13/152
摘要： The proposed method presents a novel error correction scheme utilizing LDPC codes that provides desired error floor performance. The error floor performance is achieved through combination of the two design parameters of the method. Encoding a block of user data of length S*K bits includes (A) dividing the block into S sub-blocks of equal length, each sub-block having K bits; (B) encoding each of the sub-blocks using a first Error-Correcting-Code; (C) computing bit-wise XOR of all the sub-blocks, thereby generating a new sub-block of K bits; and (D) encoding the new sub-block using a second Error-Correcting-Code.
摘要翻译：所提出的方法提出了一种利用提供期望误差底层性能的LDPC码的新颖的纠错方案。通过组合该方法的两个设计参数来实现误差平台性能。编码长度为S * K比特的用户数据块包括（A）将块划分为S个等于长度的子块，每个子块具有K个比特; （B）使用第一错误校正码对每个子块进行编码; （C）计算所有子块的逐位XOR，由此产生一个新的K位子块; 和（D）使用第二个错误校正码对新的子块进行编码。

9. 发明授权

US08892966B2 Methods and apparatus for soft data generation for memory devices using decoder performance feedback 有权
标题翻译：用于使用解码器性能反馈的存储器件的软数据生成的方法和装置
公开(公告)号：US08892966B2
公开(公告)日：2014-11-18
申请号：US13063899
申请日：2009-09-30
申请人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Clifton Williamson , Johnson Yen
发明人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Clifton Williamson , Johnson Yen
IPC分类号： G06F11/00 , G11C29/00 , G11C7/04 , G11C16/04 , G11C16/26 , G11C7/02 , G11C16/34 , G11C11/56
CPC分类号： G11C16/26 , G06F11/1012 , G06F11/1068 , G06F12/0246 , G06F2212/1032 , G06F2212/2022 , G11C7/02 , G11C7/04 , G11C11/16 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C2211/5634
摘要： Methods and apparatus for soft data generation for memory devices using decoder performance feedback. At least one soft data value is generated in a memory device, by obtaining performance feedback from a decoder; obtaining an error statistic based on the performance feedback; and generating the at least one soft data value based on the obtained error statistic. The performance feedback comprises one or more of decoded bits, a number of erroneous bits based on data decoded by the decoder and a number of unsatisfied parity checks.
摘要翻译：用于使用解码器性能反馈的存储器件的软数据生成的方法和装置。通过从解码器获得性能反馈，在存储器件中产生至少一个软数据值; 基于性能反馈获得误差统计; 以及基于所获得的误差统计量生成所述至少一个软数据值。性能反馈包括解码比特中的一个或多个，基于由解码器解码的数据的多个错误比特和多个不满足的奇偶校验。

10. 发明授权

US08429500B2 Methods and apparatus for computing a probability value of a received value in communication or storage systems 有权
标题翻译：用于计算通信或存储系统中的接收值的概率值的方法和装置
公开(公告)号：US08429500B2
公开(公告)日：2013-04-23
申请号：US12751960
申请日：2010-03-31
申请人： Erich F. Haratsch , Nenad Miladinovic , Andrei Vityaev
发明人： Erich F. Haratsch , Nenad Miladinovic , Andrei Vityaev
IPC分类号： G11C29/00
CPC分类号： H03M13/612 , H03M13/1102 , H03M13/2957 , H03M13/3905 , H03M13/41 , H03M13/4138 , H04L1/005
摘要： Methods and apparatus are provided for computing a probability value of a received value in communication or storage systems. A probability value for a received value in a communication system or a memory device is computed by obtaining at least one received value; identifying a segment of a function corresponding to the received value, wherein the function is defined over a plurality of segments, wherein each of the segments has an associated set of parameters; and calculating the probability value using the set of parameters associated with the identified segment. A probability value for a received value in a communication system or a memory device can also be computed by calculating the probability value for the received value using a first distribution, wherein the first distribution is predefined and wherein a mapped version of the first distribution approximates a distribution of the received values and wherein the calculating step is implemented by a processor, a controller, a read channel, a signal processing unit or a decoder.
摘要翻译：提供了用于计算通信或存储系统中的接收值的概率值的方法和装置。通过获得至少一个接收值来计算通信系统或存储设备中的接收值的概率值; 识别对应于所接收的值的功能的片段，其中所述功能在多个片段上被定义，其中所述片段中的每个片段具有相关联的参数组; 以及使用与所识别的段相关联的参数集来计算概率值。也可以通过使用第一分布计算接收值的概率值来计算通信系统或存储器件中的接收值的概率值，其中第一分布是预定义的，并且其中第一分布的映射版本近似于分配接收值，其中计算步骤由处理器，控制器，读通道，信号处理单元或解码器来实现。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式