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1. 发明授权

US08583720B2 Reconfigurable networked processing elements partial differential equations system 失效
标题翻译：可重构网络处理元件偏微分方程组
公开(公告)号：US08583720B2
公开(公告)日：2013-11-12
申请号：US12703513
申请日：2010-02-10
申请人： Antone Kusmanoff , Matthew P. DeLaquil , Deepak Prasanna , Jerry W. Yancey
发明人： Antone Kusmanoff , Matthew P. DeLaquil , Deepak Prasanna , Jerry W. Yancey
IPC分类号： G06F7/38 , G06F17/22
CPC分类号： G06F17/13
摘要： A method for using a system to compute a solution to a partial differential equation (PDE) broadly comprises the steps of determining the true accuracy required (TAR) to solve the PDE, determining an architecture according to the TAR that performs a plurality of calculations to solve the PDE, determining a time allowed (TA) and a time required (TR) based on the architecture to solve the PDE, rejecting the PDE if the TR is less than or equal to the TA, configuring a plurality of programmable devices with the architecture, initiating the calculations, and ceasing the calculations when an accuracy criteria is met or when the TA expires. The system broadly comprises a plurality of programmable devices, a plurality of storage elements, a device bus, a plurality of printed circuit (PC) boards, and a board to board bus.
摘要翻译：一种用于使用系统来计算偏微分方程（PDE）的解的方法广泛地包括以下步骤：确定所需的真实精度（TAR）以解决PDE，根据执行多个计算的TAR确定架构，解决PDE，基于解决PDE的架构来确定允许的时间（TA）和所需时间（TR），如果TR小于或等于TA则拒绝PDE，配置多个可编程设备架构，启动计算，并在满足准确性标准或TA到期时停止计算。该系统广泛地包括多个可编程设备，多个存储元件，设备总线，多个印刷电路板（PC）板以及板对板总线。

2. 发明申请

US20110196907A1 RECONFIGURABLE NETWORKED PROCESSING ELEMENTS PARTIAL DIFFERENTIAL EQUATIONS SYSTEM 失效
标题翻译：可重构网络处理元件部分差分方程系统
公开(公告)号：US20110196907A1
公开(公告)日：2011-08-11
申请号：US12703513
申请日：2010-02-10
申请人： Antone Kusmanoff , Matthew P. DeLaquil , Deepak Prasanna , Jerry W. Yancey
发明人： Antone Kusmanoff , Matthew P. DeLaquil , Deepak Prasanna , Jerry W. Yancey
IPC分类号： G06F17/11
CPC分类号： G06F17/13
摘要： A method for using a system to compute a solution to a partial differential equation (PDE) broadly comprises the steps of determining the true accuracy required (TAR) to solve the PDE, determining an architecture according to the TAR that performs a plurality of calculations to solve the PDE, determining a time allowed (TA) and a time required (TR) based on the architecture to solve the PDE, rejecting the PDE if the TR is less than or equal to the TA, configuring a plurality of programmable devices with the architecture, initiating the calculations, and ceasing the calculations when an accuracy criteria is met or when the TA expires. The system broadly comprises a plurality of programmable devices, a plurality of storage elements, a device bus, a plurality of printed circuit (PC) boards, and a board to board bus.
摘要翻译：一种用于使用系统来计算偏微分方程（PDE）的解的方法广泛地包括以下步骤：确定所需的真实精度（TAR）以解决PDE，根据执行多个计算的TAR确定架构，解决PDE，基于解决PDE的架构来确定允许的时间（TA）和所需时间（TR），如果TR小于或等于TA则拒绝PDE，配置多个可编程设备架构，启动计算，并在满足准确性标准或TA到期时停止计算。该系统广泛地包括多个可编程设备，多个存储元件，设备总线，多个印刷电路板（PC）板以及板对板总线。

3. 发明申请

US20100164680A1 SYSTEM AND METHOD FOR IDENTIFYING PEOPLE 审中-公开
标题翻译：用于识别人的系统和方法
公开(公告)号：US20100164680A1
公开(公告)日：2010-07-01
申请号：US12347180
申请日：2008-12-31
申请人： Jerry W. Yancey , Valentin Francisco Gavito, JR. , Aya Nagao Bennett , Deepak Prasanna , Matthew P. DeLaquil
发明人： Jerry W. Yancey , Valentin Francisco Gavito, JR. , Aya Nagao Bennett , Deepak Prasanna , Matthew P. DeLaquil
IPC分类号： G08B23/00 , G08B29/00
CPC分类号： G07C9/00103 , G07C9/00111 , G07C2009/00095
摘要： A system for identifying a person includes at least one biometric sensor for sensing a biometric characteristic of the person; at least one signal sensor for sensing a signal emitted from a device carried by the person; and a computing device for comparing the sensed biometric characteristic and the sensed signal to known characteristics of the person in an attempt to identify the person.
摘要翻译：用于识别人的系统包括用于感测人的生物特征的至少一个生物测定传感器; 用于感测从人携带的装置发射的信号的至少一个信号传感器; 以及用于将感测到的生物特征和感测到的信号与该人的已知特征进行比较以用于识别该人的计算装置。

4. 发明授权

US08751990B2 System for determining median values of video data 失效
标题翻译：用于确定视频数据的中值的系统
公开(公告)号：US08751990B2
公开(公告)日：2014-06-10
申请号：US12340166
申请日：2008-12-19
申请人： Matthew R. Standfield , Jim D. Allen , Juan Esteban Flores , Michael O'Neal Fox , Deepak Prasanna , Matthew P. DeLaquil
发明人： Matthew R. Standfield , Jim D. Allen , Juan Esteban Flores , Michael O'Neal Fox , Deepak Prasanna , Matthew P. DeLaquil
IPC分类号： G06F17/50
CPC分类号： G06F7/22
摘要： A system for determining the median of a plurality of data values comprises a plurality of field programmable gate arrays (FPGA), a plurality of inter FPGA links, an input router, a plurality of median modules, and a plurality of output transfer modules. Each FPGA includes a plurality of configurable logic elements and configurable storage elements from which the other components are formed. The inter FPGA link allows communication from one FPGA to another. The input router receives the plurality of data values and creates a plurality of data streams. The median module receives at least one data stream, increments a plurality of counters corresponding to a single data value within the range of data values, and determines the median by accumulating the contents of each counter. The output transfer module transfers the median to an external destination along with performance statistics of the determination of the median.
摘要翻译：用于确定多个数据值的中值的系统包括多个现场可编程门阵列（FPGA），多个FPGA间链路，输入路由器，多个中间模块和多个输出传输模块。每个FPGA包括多个可配置逻辑元件和可配置的存储元件，其中形成其它组件。 FPGA间链路允许从一个FPGA到另一个FPGA的通信。输入路由器接收多个数据值并创建多个数据流。中值模块接收至少一个数据流，在数据值的范围内增加对应于单个数据值的多个计数器，并通过累加每个计数器的内容来确定中值。输出传输模块将中值转移到外部目的地以及中位数确定的性能统计。

5. 发明申请

US20110122026A1 Scalable and/or reconfigurable beamformer systems 审中-公开
标题翻译：可扩展和/或可重新配置的波束形成系统
公开(公告)号：US20110122026A1
公开(公告)日：2011-05-26
申请号：US12592426
申请日：2009-11-24
申请人： Matthew P. DeLaquil , Charles E. Baucom , Deepak Prasanna
发明人： Matthew P. DeLaquil , Charles E. Baucom , Deepak Prasanna
IPC分类号： H01Q3/00
CPC分类号： H01Q3/2682
摘要： A scalable and/or reconfigurable true-time-delay analog beamformer system having a hierarchical distributed control architecture composed of an arbitrary number of reconfigurable and scalable units. The beamformer system may be applied to an antenna array with an arbitrary number of elements in a scalable manner and the configuration of the beamformer system may be implemented so that it is capable of reconfiguration by changing its beam-position mapping, either dynamically or at install-time. The number of beams or beam positions that are desired advantageously do not need to be known prior to the design or selection of the beamformer system.
摘要翻译：具有由任意数量的可重构和可缩放单元组成的分级分布式控制架构的可扩展和/或可重新配置的真时延迟模拟波束形成器系统。波束形成器系统可以以可扩展的方式应用于具有任意数量的元件的天线阵列，并且可以实现波束形成器系统的配置，使得其能够通过动态地或安装地改变其波束位置映射来重新配置 -时间。在设计或选择波束形成器系统之前，有利地不需要知道所期望的波束或波束位置的数量。

6. 发明授权

US08397054B2 Multi-phased computational reconfiguration 失效
标题翻译：多阶段计算重构
公开(公告)号：US08397054B2
公开(公告)日：2013-03-12
申请号：US12655182
申请日：2009-12-23
申请人： Antone L. Kusmanoff , Matthew P. DeLaquil , Deepak Prasanna
发明人： Antone L. Kusmanoff , Matthew P. DeLaquil , Deepak Prasanna
IPC分类号： G06F15/177 , G06F1/24
CPC分类号： G06F7/5324 , G06F7/00 , G06F2207/382 , G06F2207/3884
摘要： Problem solution speed may be increased by dynamically changing processing device computational hardware configuration in concert with respective mathematical phases of an algorithm to match accuracy demands at various phases of computation. Smaller but faster hardware structures may be increased in size using real-time partial or full reconfiguration of a processing device to apply the smallest and fastest possible computational structure for the needed accuracy during each of multiple computational phases.
摘要翻译：可以通过动态地改变处理设备的计算硬件配置与算法的各个数学阶段一致来增加问题解决方案的速度，以匹配各个计算阶段的精度要求。可以使用处理设备的实时部分或完全重新配置来增加更小但更快的硬件结构的大小，以在多个计算阶段中的每一个期间对所需精度应用最小且最快的计算结构。

7. 发明申请

US20110010409A1 SYSTEM FOR CONJUGATE GRADIENT LINEAR ITERATIVE SOLVERS 失效
标题翻译：用于并联梯度线性迭代解算器的系统
公开(公告)号：US20110010409A1
公开(公告)日：2011-01-13
申请号：US12498800
申请日：2009-07-07
申请人： Matthew P. DeLaquil , Deepak Prasanna , Antone L. Kusmanoff
发明人： Matthew P. DeLaquil , Deepak Prasanna , Antone L. Kusmanoff
IPC分类号： G06F7/38 , G06F7/32
CPC分类号： G06F17/12
摘要： A system for a conjugate gradient iterative linear solver that calculates the solution to a matrix equation comprises a plurality of gamma processing elements, a plurality of direction vector processing elements, a plurality of x-vector processing elements, an alpha processing element, and a beta processing element. The gamma processing elements may receive an A-matrix and a direction vector, and may calculate a q-vector and a gamma scalar. The direction vector processing elements may receive a beta scalar and a residual vector, and may calculate the direction vector. The x-vector processing elements may receive an alpha scalar, the direction vector, and the q-vector, and may calculate an x-vector and the residual vector. The alpha processing element may receive the gamma scalar and a delta scalar, and may calculate the alpha scalar. The beta processing element may receive the residual vector, and may calculate the delta scalar and the beta scalar.
摘要翻译：用于计算矩阵方程的解的共轭梯度迭代线性求解器的系统包括多个伽马处理元件，多个方向向量处理元件，多个x向量处理元件，α处理元件和β 处理元件。伽马处理元件可以接收A矩阵和方向向量，并且可以计算q向量和伽马标量。方向向量处理元件可以接收β标量和残差向量，并且可以计算方向向量。 x向量处理元件可以接收α标量，方向向量和q向量，并且可以计算x向量和残差向量。阿尔法处理元件可以接收伽马标量和三角形标量，并且可以计算阿尔法标量。 β处理单元可以接收剩余向量，并且可以计算Δ标量和β标量。

8. 发明申请

US20100157854A1 SYSTEMS AND METHODS FOR SENDING DATA PACKETS BETWEEN MULTIPLE FPGA DEVICES 有权
标题翻译：用于发送多个FPGA器件之间的数据包的系统和方法
公开(公告)号：US20100157854A1
公开(公告)日：2010-06-24
申请号：US12340094
申请日：2008-12-19
申请人： Joshua D. Anderson , Scott M. Burkart , Matthew P. DeLaquil , Deepak Prasanna
发明人： Joshua D. Anderson , Scott M. Burkart , Matthew P. DeLaquil , Deepak Prasanna
IPC分类号： H04L12/56 , H04L29/02 , H04L5/14
CPC分类号： H04L45/00 , H04L49/10 , H04L49/25
摘要： Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (“RHA”) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Dynamically-sized data packets, sized in accordance with the amount of data ready to be sent, are transferred between the devices and/or interfaces on the card.
摘要翻译：诸如现场可编程门阵列（“FPGA”）的专用集成电路（“ASIC”）器件可以使用诸如高速多吉比特串行收发器（“MGT”）连接的串行I / O连接进行互连。例如，可以采用串行I / O连接来互连一对ASIC以产生高带宽，低信号计数连接，并且以使得单个电路卡上的任何给定的一对多个ASIC器件可以与每个ASIC通信其他通过不超过一个串行数据通信链路连接步骤。可重新配置的硬件架构（“RHA”）可以被配置为包括使用高带宽分组路由器的通信基础设施，以在可能存在于单个电路卡上的多个接口和/或多个设备之间建立标准通信协议。根据准备发送的数据量大小的动态尺寸数据包在卡上的设备和/或接口之间传送。

9. 发明申请

US20110010410A1 SYSTEM FOR CONVERGENCE EVALUATION FOR STATIONARY METHOD ITERATIVE LINEAR SOLVERS 有权
标题翻译：迭代线性解算器的综合评估系统
公开(公告)号：US20110010410A1
公开(公告)日：2011-01-13
申请号：US12498808
申请日：2009-07-07
申请人： Matthew P. DeLaquil , Deepak Prasanna , Antone L. Kusmanoff
发明人： Matthew P. DeLaquil , Deepak Prasanna , Antone L. Kusmanoff
IPC分类号： G06F7/38 , G06F15/00 , G06F7/50
CPC分类号： G06F17/12
摘要： A system for evaluating the convergence to a solution for a matrix equation comprises at least one reconfigurable computing device such as a field programmable gate array (FPGA), an update storage element, a conversion element, a summation unit, and a comparator. The FPGA includes a plurality of configurable logic elements and a plurality of configurable storage elements, which are utilized to form the update storage element, the conversion element, the summation unit, and the comparator. The update storage element is configured to store a plurality of updates. The conversion element determines the absolute value of the updates. The summation unit accumulates the absolute values of the updates to produce a total sum, which is compared to a convergence factor by the comparator. Convergence is signaled when the total sum is less than the convergence factor.
摘要翻译：用于评估矩阵方程的收敛的系统包括至少一个可重构计算装置，例如现场可编程门阵列（FPGA），更新存储元件，转换元件，求和单元和比较器。 FPGA包括用于形成更新存储元件，转换元件，求和单元和比较器的多个可配置逻辑元件和多个可配置存储元件。更新存储元件被配置为存储多个更新。转换元素决定更新的绝对值。求和单元累积更新的绝对值以产生总和，其通过比较器与收敛因子进行比较。当总和小于收敛因子时，会发出收敛信号。

10. 发明申请

US20100161695A1 SYSTEM FOR DETERMINING MEDIAN VALUES OF VIDEO DATA 失效
标题翻译：用于确定视频数据中值的系统
公开(公告)号：US20100161695A1
公开(公告)日：2010-06-24
申请号：US12340166
申请日：2008-12-19
申请人： Matthew R. Standfield , Jim D. Allen , Juan Esteban Flores , Michael O'Neal Fox , Deepak Prasanna , Matthew P. DeLaquil
发明人： Matthew R. Standfield , Jim D. Allen , Juan Esteban Flores , Michael O'Neal Fox , Deepak Prasanna , Matthew P. DeLaquil
IPC分类号： G06F7/00 , G06F7/50 , G06F7/52
CPC分类号： G06F7/22
摘要： A system for determining the median of a plurality of data values comprises a plurality of field programmable gate arrays (FPGA), a plurality of inter FPGA links, an input router, a plurality of median modules, and a plurality of output transfer modules. Each FPGA includes a plurality of configurable logic elements and configurable storage elements from which the other components are formed. The inter FPGA link allows communication from one FPGA to another. The input router receives the plurality of data values and creates a plurality of data streams. The median module receives at least one data stream, increments a plurality of counters corresponding to a single data value within the range of data values, and determines the median by accumulating the contents of each counter. The output transfer module transfers the median to an external destination along with performance statistics of the determination of the median.
摘要翻译：用于确定多个数据值的中值的系统包括多个现场可编程门阵列（FPGA），多个FPGA间链路，输入路由器，多个中间模块和多个输出传输模块。每个FPGA包括多个可配置逻辑元件和可配置的存储元件，其中形成其它组件。 FPGA间链路允许从一个FPGA到另一个FPGA的通信。输入路由器接收多个数据值并创建多个数据流。中值模块接收至少一个数据流，在数据值的范围内增加对应于单个数据值的多个计数器，并通过累加每个计数器的内容来确定中值。输出传输模块将中值转移到外部目的地以及中位数确定的性能统计。

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