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1. 发明授权

US09176928B2 System for convergence evaluation for stationary method iterative linear solvers 有权
标题翻译：用于固定方法迭代线性求解器的收敛估计系统
公开(公告)号：US09176928B2
公开(公告)日：2015-11-03
申请号：US12498808
申请日：2009-07-07
申请人： Matthew P. DeLaquil , Deepak Prasanna , Antone L. Kusmanoff
发明人： Matthew P. DeLaquil , Deepak Prasanna , Antone L. Kusmanoff
IPC分类号： G06F17/14 , G06F7/38 , G06F7/32 , H03M13/00 , G06F17/12
CPC分类号： G06F17/12
摘要： A system for evaluating the convergence to a solution for a matrix equation comprises at least one reconfigurable computing device such as a field programmable gate array (FPGA), an update storage element, a conversion element, a summation unit, and a comparator. The FPGA includes a plurality of configurable logic elements and a plurality of configurable storage elements, which are utilized to form the update storage element, the conversion element, the summation unit, and the comparator. The update storage element is configured to store a plurality of updates. The conversion element determines the absolute value of the updates. The summation unit accumulates the absolute values of the updates to produce a total sum, which is compared to a convergence factor by the comparator. Convergence is signaled when the total sum is less than the convergence factor.
摘要翻译：用于评估矩阵方程的收敛的系统包括至少一个可重构计算装置，例如现场可编程门阵列（FPGA），更新存储元件，转换元件，求和单元和比较器。 FPGA包括用于形成更新存储元件，转换元件，求和单元和比较器的多个可配置逻辑元件和多个可配置存储元件。更新存储元件被配置为存储多个更新。转换元素决定更新的绝对值。求和单元累积更新的绝对值以产生总和，其通过比较器与收敛因子进行比较。当总和小于收敛因子时，会发出收敛信号。

2. 发明申请

US20110154012A1 Multi-phased computational reconfiguration 失效
标题翻译：多阶段计算重构
公开(公告)号：US20110154012A1
公开(公告)日：2011-06-23
申请号：US12655182
申请日：2009-12-23
申请人： Antone L. Kusmanoff , Matthew P. DeLaquil , Deepak Prasanna
发明人： Antone L. Kusmanoff , Matthew P. DeLaquil , Deepak Prasanna
IPC分类号： G06F9/24
CPC分类号： G06F7/5324 , G06F7/00 , G06F2207/382 , G06F2207/3884
摘要： Problem solution speed may be increased by dynamically changing processing device computational hardware configuration in concert with respective mathematical phases of an algorithm to match accuracy demands at various phases of computation. Smaller but faster hardware structures may be increased in size using real-time partial or full reconfiguration of a processing device to apply the smallest and fastest possible computational structure for the needed accuracy during each of multiple computational phases.
摘要翻译：可以通过动态地改变处理设备的计算硬件配置与算法的各个数学阶段一致来增加问题解决方案的速度，以匹配各个计算阶段的精度要求。可以使用处理设备的实时部分或完全重新配置来增加更小但更快的硬件结构的大小，以在多个计算阶段中的每一个期间对所需精度应用最小且最快的计算结构。

3. 发明授权

US08577949B2 System for conjugate gradient linear iterative solvers 失效
标题翻译：共轭梯度线性迭代求解器系统
公开(公告)号：US08577949B2
公开(公告)日：2013-11-05
申请号：US12498800
申请日：2009-07-07
申请人： Matthew P. DeLaquil , Deepak Prasanna , Antone L. Kusmanoff
发明人： Matthew P. DeLaquil , Deepak Prasanna , Antone L. Kusmanoff
IPC分类号： G06F7/48 , G06F7/00 , G06F7/38 , G06F17/14 , G06F7/32 , G06F7/52 , G06F7/60
CPC分类号： G06F17/12
摘要： A system for a conjugate gradient iterative linear solver that calculates the solution to a matrix equation comprises a plurality of gamma processing elements, a plurality of direction vector processing elements, a plurality of x-vector processing elements, an alpha processing element, and a beta processing element. The gamma processing elements may receive an A-matrix and a direction vector, and may calculate a q-vector and a gamma scalar. The direction vector processing elements may receive a beta scalar and a residual vector, and may calculate the direction vector. The x-vector processing elements may receive an alpha scalar, the direction vector, and the q-vector, and may calculate an x-vector and the residual vector. The alpha processing element may receive the gamma scalar and a delta scalar, and may calculate the alpha scalar. The beta processing element may receive the residual vector, and may calculate the delta scalar and the beta scalar.
摘要翻译：用于计算矩阵方程的解的共轭梯度迭代线性求解器的系统包括多个伽马处理元件，多个方向向量处理元件，多个x向量处理元件，α处理元件和β 处理元件。伽马处理元件可以接收A矩阵和方向向量，并且可以计算q向量和伽马标量。方向向量处理元件可以接收β标量和残差向量，并且可以计算方向向量。 x向量处理元件可以接收α标量，方向向量和q向量，并且可以计算x向量和残差向量。阿尔法处理元件可以接收伽马标量和三角形标量，并且可以计算阿尔法标量。 β处理单元可以接收剩余向量，并且可以计算Δ标量和β标量。

4. 发明申请

US20110010410A1 SYSTEM FOR CONVERGENCE EVALUATION FOR STATIONARY METHOD ITERATIVE LINEAR SOLVERS 有权
标题翻译：迭代线性解算器的综合评估系统
公开(公告)号：US20110010410A1
公开(公告)日：2011-01-13
申请号：US12498808
申请日：2009-07-07
申请人： Matthew P. DeLaquil , Deepak Prasanna , Antone L. Kusmanoff
发明人： Matthew P. DeLaquil , Deepak Prasanna , Antone L. Kusmanoff
IPC分类号： G06F7/38 , G06F15/00 , G06F7/50
CPC分类号： G06F17/12
摘要： A system for evaluating the convergence to a solution for a matrix equation comprises at least one reconfigurable computing device such as a field programmable gate array (FPGA), an update storage element, a conversion element, a summation unit, and a comparator. The FPGA includes a plurality of configurable logic elements and a plurality of configurable storage elements, which are utilized to form the update storage element, the conversion element, the summation unit, and the comparator. The update storage element is configured to store a plurality of updates. The conversion element determines the absolute value of the updates. The summation unit accumulates the absolute values of the updates to produce a total sum, which is compared to a convergence factor by the comparator. Convergence is signaled when the total sum is less than the convergence factor.
摘要翻译：用于评估矩阵方程的收敛的系统包括至少一个可重构计算装置，例如现场可编程门阵列（FPGA），更新存储元件，转换元件，求和单元和比较器。 FPGA包括用于形成更新存储元件，转换元件，求和单元和比较器的多个可配置逻辑元件和多个可配置存储元件。更新存储元件被配置为存储多个更新。转换元素决定更新的绝对值。求和单元累积更新的绝对值以产生总和，其通过比较器与收敛因子进行比较。当总和小于收敛因子时，会发出收敛信号。

5. 发明授权

US08397054B2 Multi-phased computational reconfiguration 失效
标题翻译：多阶段计算重构
公开(公告)号：US08397054B2
公开(公告)日：2013-03-12
申请号：US12655182
申请日：2009-12-23
申请人： Antone L. Kusmanoff , Matthew P. DeLaquil , Deepak Prasanna
发明人： Antone L. Kusmanoff , Matthew P. DeLaquil , Deepak Prasanna
IPC分类号： G06F15/177 , G06F1/24
CPC分类号： G06F7/5324 , G06F7/00 , G06F2207/382 , G06F2207/3884
摘要： Problem solution speed may be increased by dynamically changing processing device computational hardware configuration in concert with respective mathematical phases of an algorithm to match accuracy demands at various phases of computation. Smaller but faster hardware structures may be increased in size using real-time partial or full reconfiguration of a processing device to apply the smallest and fastest possible computational structure for the needed accuracy during each of multiple computational phases.
摘要翻译：可以通过动态地改变处理设备的计算硬件配置与算法的各个数学阶段一致来增加问题解决方案的速度，以匹配各个计算阶段的精度要求。可以使用处理设备的实时部分或完全重新配置来增加更小但更快的硬件结构的大小，以在多个计算阶段中的每一个期间对所需精度应用最小且最快的计算结构。

6. 发明申请

US20110010409A1 SYSTEM FOR CONJUGATE GRADIENT LINEAR ITERATIVE SOLVERS 失效
标题翻译：用于并联梯度线性迭代解算器的系统
公开(公告)号：US20110010409A1
公开(公告)日：2011-01-13
申请号：US12498800
申请日：2009-07-07
申请人： Matthew P. DeLaquil , Deepak Prasanna , Antone L. Kusmanoff
发明人： Matthew P. DeLaquil , Deepak Prasanna , Antone L. Kusmanoff
IPC分类号： G06F7/38 , G06F7/32
CPC分类号： G06F17/12
摘要： A system for a conjugate gradient iterative linear solver that calculates the solution to a matrix equation comprises a plurality of gamma processing elements, a plurality of direction vector processing elements, a plurality of x-vector processing elements, an alpha processing element, and a beta processing element. The gamma processing elements may receive an A-matrix and a direction vector, and may calculate a q-vector and a gamma scalar. The direction vector processing elements may receive a beta scalar and a residual vector, and may calculate the direction vector. The x-vector processing elements may receive an alpha scalar, the direction vector, and the q-vector, and may calculate an x-vector and the residual vector. The alpha processing element may receive the gamma scalar and a delta scalar, and may calculate the alpha scalar. The beta processing element may receive the residual vector, and may calculate the delta scalar and the beta scalar.
摘要翻译：用于计算矩阵方程的解的共轭梯度迭代线性求解器的系统包括多个伽马处理元件，多个方向向量处理元件，多个x向量处理元件，α处理元件和β 处理元件。伽马处理元件可以接收A矩阵和方向向量，并且可以计算q向量和伽马标量。方向向量处理元件可以接收β标量和残差向量，并且可以计算方向向量。 x向量处理元件可以接收α标量，方向向量和q向量，并且可以计算x向量和残差向量。阿尔法处理元件可以接收伽马标量和三角形标量，并且可以计算阿尔法标量。 β处理单元可以接收剩余向量，并且可以计算Δ标量和β标量。

7. 发明申请

US20100159866A1 Systems and methods for interference cancellation 有权
标题翻译：用于干扰消除的系统和方法
公开(公告)号：US20100159866A1
公开(公告)日：2010-06-24
申请号：US12317486
申请日：2008-12-23
申请人： Gerald L. Fudge , Ross E. Bland , Antone L. Kusmanoff
发明人： Gerald L. Fudge , Ross E. Bland , Antone L. Kusmanoff
IPC分类号： H04B1/10
CPC分类号： H04B1/1036
摘要： Systems and methods for interference cancellation in which a first signal having a first frequency may be cancelled with a second frequency having a second and different (e.g., lower) frequency by employing sampling to cancel the first signal with the separate signal at the sample instances.
摘要翻译：用于干扰消除的系统和方法，其中具有第一频率的第一信号可以用具有第二频率和第二频率的第二频率通过采样采样来取消，所述第二频率具有第二和不同（例如，较低）频率，以利用采样情况下的分离信号来取消第一信号。

8. 发明授权

US08401050B1 Multiple projection sampling for RF sampling receivers 有权
标题翻译：射频采样接收机的多重投影采样
公开(公告)号：US08401050B1
公开(公告)日：2013-03-19
申请号：US13048489
申请日：2011-03-15
申请人： Gerald L. Fudge , Scott M. Burkart , Antone L. Kusmanoff
发明人： Gerald L. Fudge , Scott M. Burkart , Antone L. Kusmanoff
IPC分类号： H04B1/00
CPC分类号： H04B1/0014
摘要： RF sampling receivers are disclosed that employ multiple sampling clocks to produce multiple projections. In operation, a Nyquist folded receiver (NYFR) may be implemented that utilizes at least one modulated sampling clock in combination with one or more other modulated or non-modulated sampling clocks to identify received signals. In such an embodiment, one or more clock modulations may be used to induce frequency modulations that are Nyquist zone dependent, and multiple Nyquist zones may be aliased together while still allowing for signals from different Nyquist zones to be separated and identified.
摘要翻译：公开了采用多个采样时钟来产生多个投影的RF采样接收器。在操作中，可以实现奈奎斯特折叠接收器（NYFR），其利用与一个或多个其他调制或非调制采样时钟组合的至少一个调制采样时钟来识别接收到的信号。在这样的实施例中，可以使用一个或多个时钟调制来诱导奈奎斯特区域相关的频率调制，并且可以将多个奈奎斯特区域混叠在一起，同时允许来自不同奈奎斯特区域的信号被分离和识别。

9. 发明授权

US08078130B2 Systems and methods for interference cancellation 有权
标题翻译：用于干扰消除的系统和方法
公开(公告)号：US08078130B2
公开(公告)日：2011-12-13
申请号：US12317486
申请日：2008-12-23
申请人： Gerald L. Fudge , Ross E. Bland , Antone L. Kusmanoff
发明人： Gerald L. Fudge , Ross E. Bland , Antone L. Kusmanoff
IPC分类号： H04B1/10
CPC分类号： H04B1/1036
摘要： Systems and methods for interference cancellation in which a first signal having a first frequency may be cancelled with a second frequency having a second and different (e.g., lower) frequency by employing sampling to cancel the first signal with the separate signal at the sample instances.
摘要翻译：用于干扰消除的系统和方法，其中具有第一频率的第一信号可以用具有第二频率和第二频率的第二频率通过采样采样来取消，所述第二频率具有第二和不同（例如，较低）频率，以利用采样情况下的分离信号来取消第一信号。

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