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1. 发明授权

US09153547B2 Integrated inductor structure and method of fabrication 有权
标题翻译：集成电感器结构及其制造方法
公开(公告)号：US09153547B2
公开(公告)日：2015-10-06
申请号：US12428430
申请日：2009-04-22
申请人： Ankur Mohan Crawford , Henning Braunisch , Rajendran Nair , Gilroy Vandentop , Shan X. Wang
发明人： Ankur Mohan Crawford , Henning Braunisch , Rajendran Nair , Gilroy Vandentop , Shan X. Wang
IPC分类号： H01F5/00 , H01F27/28 , H01L27/08 , H01F7/06 , H01L23/64 , H01F17/00 , H01F41/04 , H01L23/498 , H01L49/02 , H05K1/03 , H05K1/16 , H05K3/46
CPC分类号： H01L23/645 , H01F17/0033 , H01F41/046 , H01L23/49822 , H01L28/10 , H01L2224/16 , H01L2224/16235 , H01L2924/00011 , H01L2924/00014 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311 , H01L2924/15312 , H01L2924/3011 , H05K1/0373 , H05K1/165 , H05K3/4644 , H05K2201/086 , H05K2201/09563 , H01L2224/0401
摘要： An inductor structure comprised of a magnetic section and a single turn solenoid. The single turn solenoid to contain within a portion of the magnetic section and circumscribed by the magnetic section.
摘要翻译：一个电感结构由一个磁性部分和一个单一的旋转螺线管组成。单转螺线管包含在磁性部分的一部分内并由磁性部分限定。

2. 发明申请

US20090201113A1 INTEGRATED INDUCTOR STRUCTURE AND METHOD OF FABRICATION 有权
标题翻译：综合电感结构与制造方法
公开(公告)号：US20090201113A1
公开(公告)日：2009-08-13
申请号：US12428430
申请日：2009-04-22
申请人： Ankur Mohan Crawford , Henning Braunisch , Rajendran Nair , Gilroy Vandentop , Shan X. Wang
发明人： Ankur Mohan Crawford , Henning Braunisch , Rajendran Nair , Gilroy Vandentop , Shan X. Wang
IPC分类号： H01F21/02 , H01F17/04
CPC分类号： H01L23/645 , H01F17/0033 , H01F41/046 , H01L23/49822 , H01L28/10 , H01L2224/16 , H01L2224/16235 , H01L2924/00011 , H01L2924/00014 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311 , H01L2924/15312 , H01L2924/3011 , H05K1/0373 , H05K1/165 , H05K3/4644 , H05K2201/086 , H05K2201/09563 , H01L2224/0401
摘要： An inductor structure comprised of a magnetic section and a single turn solenoid. The single turn solenoid to contain within a portion of the magnetic section and circumscribed by the magnetic section.
摘要翻译：一个电感结构，由一个磁性部分和一个单一的旋转螺线管组成。单转螺线管包含在磁性部分的一部分内并由磁性部分限定。

3. 发明申请

US20070069333A1 INTEGRATED INDUCTOR STRUCTURE AND METHOD OF FABRICATION 审中-公开
标题翻译：综合电感结构与制造方法
公开(公告)号：US20070069333A1
公开(公告)日：2007-03-29
申请号：US11554567
申请日：2006-10-30
申请人： Ankur Crawford , Henning Braunisch , Rajendran Nair , Gilroy Vandentop , Shan Wang
发明人： Ankur Crawford , Henning Braunisch , Rajendran Nair , Gilroy Vandentop , Shan Wang
IPC分类号： H01L29/00
CPC分类号： H01L23/645 , H01F17/0033 , H01F41/046 , H01L23/49822 , H01L28/10 , H01L2224/16 , H01L2224/16235 , H01L2924/00011 , H01L2924/00014 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311 , H01L2924/15312 , H01L2924/3011 , H05K1/0373 , H05K1/165 , H05K3/4644 , H05K2201/086 , H05K2201/09563 , H01L2224/0401
摘要： An inductor structure comprised of a magnetic section and a single turn solenoid The single turn solenoid to contain within a portion of the magnetic section and circumscribed by the magnetic section.
摘要翻译：由磁性部分和单匝螺线管组成的电感器结构单转螺线管包含在磁性部分的一部分内并由磁性部分限定。

4. 发明申请

US20060088971A1 Integrated inductor and method of fabrication 审中-公开
标题翻译：集成电感和制造方法
公开(公告)号：US20060088971A1
公开(公告)日：2006-04-27
申请号：US10975552
申请日：2004-10-27
申请人： Ankur Crawford , Henning Braunisch , Rajendran Nair , Gilroy Vandentop , Shan Wang
发明人： Ankur Crawford , Henning Braunisch , Rajendran Nair , Gilroy Vandentop , Shan Wang
IPC分类号： H01L21/20
CPC分类号： H01L23/645 , H01F17/0033 , H01F41/046 , H01L23/49822 , H01L28/10 , H01L2224/16 , H01L2224/16235 , H01L2924/00011 , H01L2924/00014 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311 , H01L2924/15312 , H01L2924/3011 , H05K1/0373 , H05K1/165 , H05K3/4644 , H05K2201/086 , H05K2201/09563 , H01L2224/0401
摘要： An inductor structure comprised of a magnetic section and a single turn solenoid. The single turn solenoid to contain within a portion of the magnetic section and circumscribed by the magnetic section.
摘要翻译：一个电感结构由一个磁性部分和一个单一的旋转螺线管组成。单转螺线管包含在磁性部分的一部分内并由磁性部分限定。

5. 发明授权

US08563865B2 Flat wire shielded pair and cable 失效
标题翻译：扁平线屏蔽对和电缆
公开(公告)号：US08563865B2
公开(公告)日：2013-10-22
申请号：US13200974
申请日：2011-10-06
申请人： Rajendran Nair
发明人： Rajendran Nair
IPC分类号： H01B11/00 , H01B7/18
CPC分类号： H01B7/0876
摘要： Novel shielded flat wire pair and cable implement flat, smooth conductors coated with insulation bonded together, providing rectangular cross-sections and equidistant, smooth surfaces for high frequency signal current flow. Flat wire pairs with conductive covers and symmetrically placed shield conductors in grooves between flat wires minimize intra-pair signal flow skew. Shielded flat wire pairs are placed within a cable assembly with adjacent wire pairs oriented orthogonally, minimizing crosstalk and rendering crosstalk common-mode. Such orientation of flat wire pairs is assisted by an internal separator, which may be electrically conductive and grounded providing enhanced pair to pair isolation. Presence of flat wire pairs and an internal separator in a cable positions additional single wires in the cable firmly against a grounded external shield, ensuring a predetermined impedance for these signal wires. Shielded flat wire pairs and cables of low metal content extend electrical signaling to the millimeter wave regimes.
摘要翻译：新型屏蔽扁平线对和电缆实现平坦，平滑的导体，绝缘粘合在一起，提供矩形横截面和等距，平滑的表面，用于高频信号电流流动。具有导电覆盖物的扁平线对和在扁平线之间的沟槽中的对称放置的屏蔽导体使得对内信号流偏移最小化。屏蔽扁平线对放置在具有正交定向的相邻线对的电缆组件内，最小化串扰并呈现串扰共模。扁平线对的这种取向由内部分离器辅助，其可以是导电的和接地的，从而提供增强的对对对隔离。电缆线和电缆内部分离器的存在将电缆中的额外单根电线牢固地固定在接地的外部屏蔽上，确保这些信号线的预定阻抗。屏蔽扁平线对和低金属含量的电缆将电信号传输到毫米波方案。

6. 发明授权

US06849909B1 Method and apparatus for weak inversion mode MOS decoupling capacitor 失效
标题翻译：弱反转模式MOS去耦电容器的方法和装置
公开(公告)号：US06849909B1
公开(公告)日：2005-02-01
申请号：US09677698
申请日：2000-09-28
申请人： Rajendran Nair , Siva G. Narendra , Tanay Karnik , Vivek K. De
发明人： Rajendran Nair , Siva G. Narendra , Tanay Karnik , Vivek K. De
IPC分类号： H01L27/08 , H01L31/119 , H01L29/088 , H01L29/90
CPC分类号： H01L27/0811 , Y10S257/901
摘要： A method and apparatus for providing a weak inversion mode metal-oxide-semiconductor (MOS) decoupling capacitor is described. In one embodiment, an enhancement-mode p-channel MOS (PMOS) transistor is constructed with a gate material whose work function differs from that commonly used. In one exemplary embodiment, platinum silicate (PtSi) is used. In alternate embodiments, the threshold voltage of the PMOS transistor may be changed by modifying the dopant levels of the substrate. In either embodiment the flat band magnitude of the transistor is shifted by the change in materials used to construct the transistor. When such a transistor is connected with the gate lead connected to the positive supply voltage and the other leads connected to the negative (ground) supply voltage, an improved decoupling capacitor results.
摘要翻译：描述了用于提供弱反型模式金属氧化物半导体（MOS）去耦电容器的方法和装置。在一个实施例中，增强型p沟道MOS（PMOS）晶体管由其功能与常用功能不同的栅极材料构成。在一个示例性实施方案中，使用铂硅酸盐（PtSi）。在替代实施例中，可以通过修改衬底的掺杂剂水平来改变PMOS晶体管的阈值电压。在任一实施例中，晶体管的平带幅度偏移用于构造晶体管的材料的变化。当这种晶体管与连接到正电源电压的栅极引线连接，而其他引线连接到负（接地）电源电压时，会产生改进的去耦电容。

7. 发明授权

US06529398B1 Ferroelectric memory and method for reading the same 失效
标题翻译：铁电存储器及其读取方法
公开(公告)号：US06529398B1
公开(公告)日：2003-03-04
申请号：US09967495
申请日：2001-09-27
申请人： Rajendran Nair , David G. Chow
发明人： Rajendran Nair , David G. Chow
IPC分类号： G11C1112
CPC分类号： G11C11/22
摘要： A ferroelectric memory device and method for reading such a device utilize capacitive coupling between a reference circuit and a sense amplifier. The amount of sneak charge canceled from a data bit line depends on the relative capacitances of a coupling capacitor and another capacitor used to integrate sneak charge from a reference bit line. The use of linear-responding components improves stability.
摘要翻译：用于读取这种器件的铁电存储器件和方法利用参考电路和读出放大器之间的电容耦合。从数据位线取消的潜行电荷量取决于耦合电容器和用于集成来自参考位线的潜行电荷的另一个电容器的相对电容。线性响应元件的使用提高了稳定性。

8. 发明申请

US20080308294A1 Swizzled twisted pair cable for simultaneous skew and crosstalk minimization 审中-公开
标题翻译：旋转双绞线用于同时扭曲和串扰最小化
公开(公告)号：US20080308294A1
公开(公告)日：2008-12-18
申请号：US11818127
申请日：2007-06-14
申请人： Rajendran Nair
发明人： Rajendran Nair
IPC分类号： H01B11/02
CPC分类号： H01B11/002
摘要： A novel varied twist-rate wire pair and cable architecture are disclosed. The invention implements variable twist rate along twisted wire pair length, providing approximately equivalent physical and electrical length values for segments of such twisted wire pair, and consequently, low delay skew, and substantially minimized inter-pair crosstalk due to reduction of twist-rate correlation along the length of a UTP cable employing the invention. Due to the elimination of the need for shielding, the invention method yields flexible, low-cost cables that may be employed for extremely high data throughput applications such as HDMI. Minimized inter-pair skew also eliminates the need for channel re-alignment at the end of long cable runs. Through these benefits, the invention twisted pair and cable facilitates continued enhancements in multi-media electronics while containing cost for high-performance interconnect.
摘要翻译：公开了一种新颖的扭曲线对和电缆结构。本发明实现了沿双绞线长度的可变扭转速率，为这种双绞线对的段提供大致相等的物理和电长度值，因此由于扭转速率相关性的降低而导致低延迟偏差和基本上最小化的对 - 串扰沿着使用本发明的UTP电缆的长度。由于消除了对屏蔽的需要，本发明方法产生可用于诸如HDMI之类的极高数据吞吐量应用的灵活的低成本电缆。最小化的对间偏斜也消除了在长电缆运行结束时对通道重新对准的需要。通过这些优点，本发明的双绞线和电缆有助于多媒体电子设备的持续增强，同时还包含高性能互连的成本。

9. 发明授权

US07405364B2 Decoupled signal-power substrate architecture 有权
标题翻译：解耦信号功率基板架构
公开(公告)号：US07405364B2
公开(公告)日：2008-07-29
申请号：US10335026
申请日：2002-12-30
申请人： Rajendran Nair , John Tang
发明人： Rajendran Nair , John Tang
IPC分类号： H05K3/30 , H05K1/16
CPC分类号： H01L23/50 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L2224/16225 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/15312 , H01L2924/19106 , H01L2924/3011 , H05K1/147 , H05K3/4602 , H05K2201/09309 , H05K2201/10681 , Y10T29/49126 , Y10T29/4913 , H01L2924/00 , H01L2224/0401
摘要： A device comprises a substrate core having power paths through it and an input/output signal routing layer upon the core substrate. An integrated circuit may be arranged on the routing layer such that the integrated circuit is electrically coupled to the substrate core through the routing layer.
摘要翻译：一种器件包括具有通过其的功率路径的衬底芯和在芯衬底上的输入/输出信号布线层。集成电路可以布置在路由层上，使得集成电路通过路由层电耦合到衬底核心。

10. 发明申请

US20080116943A1 True-differential DVI/HDMI line driver 审中-公开
标题翻译：真差分DVI / HDMI线路驱动器
公开(公告)号：US20080116943A1
公开(公告)日：2008-05-22
申请号：US11633879
申请日：2006-12-05
申请人： Rajendran Nair
发明人： Rajendran Nair
IPC分类号： H03K3/00
CPC分类号： H03K19/018528 , H04L25/0272 , H04L25/0282 , H04L25/085
摘要： A novel source-coupled differential driver circuit fully compatible with digital visual interface (DVI/HDMI) signaling specification is disclosed. Driven output signals are connected to the source terminals of driving switches in the invention circuit, minimizing the detrimental impact of miller coupling capacitance between gate nodes and driven output nodes upon output slew-rate, enabling higher frequencies of operation. Undriven output wires are connected to source-termination impedances, providing a matched return current to the driven current signal, and reducing return path impedance substantially. Matched differential current drive from the source ensures true-differential signaling, eliminating shield current flow and improving signal integrity. Bit error rate (BER) is reduced and overall link performance is significantly enhanced due to improved slew rates, true-differential signaling and greater signal integrity, enabling long reach and high-speed, high-definition multi-media data transmission.
摘要翻译：公开了一种与数字视频接口（DVI / HDMI）信令规范完全兼容的新颖的源极耦合差分驱动电路。驱动的输出信号连接到本发明电路中的驱动开关的源极端子，最小化输出转换速率时栅极节点和驱动输出节点之间的铣刀耦合电容的有害影响，从而实现更高的操作频率。无驱动输出线连接到源极端接阻抗，为驱动电流信号提供匹配的返回电流，并显着降低返回路径阻抗。来自源的匹配差分电流驱动器确保真实差分信号，消除屏蔽电流流动并提高信号完整性。由于改进的转换速率，真实差分信号和更大的信号完整性，可以降低误码率（BER），从而提高整体链路性能，从而实现长距离和高速，高清多媒体数据传输。

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