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1. 发明授权

US07683416B2 Post STI trench capacitor 失效
标题翻译：后STI沟槽电容器
公开(公告)号：US07683416B2
公开(公告)日：2010-03-23
申请号：US11935698
申请日：2007-11-06
申请人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
发明人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
IPC分类号： H01L27/108
CPC分类号： H01L29/94 , H01L28/91 , H01L29/66181
摘要： A design structure for capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.
摘要翻译：在由诸如凹陷隔离或浅沟槽隔离的隔离结构限定的沟槽中形成用于去耦应用的适当大值的电容器的设计结构。电容器提供与有源区域共同延伸的接触区域，并且可以单独或少量可靠地形成。板触点优选通过延伸到形成电容器板的掺杂剂扩散区域之间或之间的注入区域制成。可以通过形成隔离结构之后的过程形成电容器，使得可以使用优选的软掩模工艺来形成隔离结构和工艺共同性，并避免兼容性约束，同时电容器形成过程可以与其他处理共同执行结构。

2. 发明授权

US07682922B2 Post STI trench capacitor 失效
标题翻译：后STI沟槽电容器
公开(公告)号：US07682922B2
公开(公告)日：2010-03-23
申请号：US11624385
申请日：2007-01-18
申请人： Anil K. Chinthakindi , Deok-Kee Kim , Xi Li
发明人： Anil K. Chinthakindi , Deok-Kee Kim , Xi Li
IPC分类号： H01L21/20
CPC分类号： H01L29/94 , H01L27/0805 , H01L28/91 , H01L29/66181
摘要： A capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.
摘要翻译：在由诸如凹陷隔离或浅沟槽隔离的隔离结构限定的沟槽中形成具有用于去耦应用的适当大值的电容器。电容器提供与有源区域共同延伸的接触区域，并且可以单独或少量可靠地形成。板触点优选通过延伸到形成电容器板的掺杂剂扩散区域之间或之间的注入区域制成。可以通过形成隔离结构之后的过程形成电容器，使得可以使用优选的软掩模工艺来形成隔离结构和工艺共同性，并避免兼容性约束，同时电容器形成过程可以与其他处理共同执行结构。

3. 发明申请

US20080173918A1 Post STI Trench Capacitor 失效
标题翻译：后STI沟槽电容器
公开(公告)号：US20080173918A1
公开(公告)日：2008-07-24
申请号：US11935698
申请日：2007-11-06
申请人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
发明人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
IPC分类号： H01L29/94
CPC分类号： H01L29/94 , H01L28/91 , H01L29/66181
摘要： A design structure for capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.
摘要翻译：在由诸如凹陷隔离或浅沟槽隔离的隔离结构限定的沟槽中形成用于去耦应用的适当大值的电容器的设计结构。电容器提供与有源区域共同延伸的接触区域，并且可以单独或少量可靠地形成。板触点优选通过延伸到形成电容器板的掺杂剂扩散区域之间或之间的注入区域制成。可以通过形成隔离结构之后的过程形成电容器，使得可以使用优选的软掩模工艺来形成隔离结构和工艺共同性，并避免兼容性约束，同时电容器形成过程可以与其他处理共同执行结构。

4. 发明申请

US20080173977A1 POST STI TRENCH CAPACITOR 失效
标题翻译： POST STI TRENCH电容器
公开(公告)号：US20080173977A1
公开(公告)日：2008-07-24
申请号：US11624385
申请日：2007-01-18
申请人： Anil K. Chinthakindi , Deok-Kee Kim , Xi Li
发明人： Anil K. Chinthakindi , Deok-Kee Kim , Xi Li
IPC分类号： H01L21/02 , H01L29/92
CPC分类号： H01L29/94 , H01L27/0805 , H01L28/91 , H01L29/66181
摘要： A capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.
摘要翻译：在由诸如凹陷隔离或浅沟槽隔离的隔离结构限定的沟槽中形成具有用于去耦应用的适当大值的电容器。电容器提供与有源区域共同延伸的接触区域，并且可以单独或少量可靠地形成。板触点优选通过延伸到形成电容器板的掺杂剂扩散区域之间或之间的注入区域制成。可以通过形成隔离结构之后的过程形成电容器，使得可以使用优选的软掩模工艺来形成隔离结构和工艺共同性，并避免兼容性约束，同时电容器形成过程可以与其他处理共同执行结构。

5. 发明申请

US20080157270A1 Metal to Metal Low-K Antifuse 审中-公开
标题翻译：金属与金属Low-K防腐剂
公开(公告)号：US20080157270A1
公开(公告)日：2008-07-03
申请号：US11618757
申请日：2006-12-30
申请人： Deok-kee Kim , Anil K. Chinthakindi , Son Van Nguyen , Kelly Malone , Byeongju Park
发明人： Deok-kee Kim , Anil K. Chinthakindi , Son Van Nguyen , Kelly Malone , Byeongju Park
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： The embodiments of the invention generally relate to fuse and anti-fuse structures and include a copper conductor positioned within a substrate and a metal cap on the first conductor. A low-k dielectric is on the substrate and the metal cap. A tantalum nitride resistor is on the dielectric, and the resistor is positioned above the metal cap such that an antifuse element region of the dielectric is positioned between the resistor and the metal cap. The antifuse element region of the dielectric is adapted to change resistance values by application of a voltage difference between the resistor and the copper conductor/metal cap. The antifuse element region has a first higher resistance (more closely matching an insulator) before application of the voltage and a second lower resistance (more closely matching a conductor) after application of such voltage. In one embodiment herein the voltage can be supplemented by heating through application of voltage through the first conductor which helps change the resistance of the antifuse element region.
摘要翻译：本发明的实施例一般涉及熔丝和反熔丝结构，并且包括定位在基板内的铜导体和第一导体上的金属盖。低k电介质位于基板和金属盖上。电介质上的氮化钽电阻器，电阻器位于金属帽的上方，使得电介质的反熔丝元件区域位于电阻器和金属帽之间。电介质的反熔丝元件区域适于通过施加电阻器和铜导体/金属帽之间的电压差来改变电阻值。在施加电压之后，反熔丝元件区域具有第一高电阻（更紧密地匹配绝缘体）和施加电压之后的第二较低电阻（更接近地匹配导体）。在本文的一个实施例中，可以通过施加通过第一导体的电压进行加热来补充电压，这有助于改变反熔丝元件区域的电阻。

6. 发明授权

US07566593B2 Fuse structure including cavity and methods for fabrication thereof 失效
标题翻译：保险丝结构，包括腔体及其制造方法
公开(公告)号：US07566593B2
公开(公告)日：2009-07-28
申请号：US11538170
申请日：2006-10-03
申请人： Anil K. Chinthakindi , Deok-kee Kim , Chandrasekharan Kothandaraman
发明人： Anil K. Chinthakindi , Deok-kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure comprises a cavity interposed between a substrate and a fuse material layer. The cavity is not formed at a sidewall of the fuse material layer, or at a surface of the fuse material layer opposite the substrate. A void may be formed interposed between the substrate and the fuse material layer while using a self-aligned etching method, when the fuse material layer comprises lobed ends and a narrower middle region. The void is separated by a pair of sacrificial layer pedestals that support the fuse material layer. The void is encapsulated to form the cavity by using an encapsulating dielectric layer. Alternatively, a block mask may be used when forming the void interposed between the substrate and the fuse material layer.
摘要翻译：熔丝结构包括插入在基板和熔丝材料层之间的空腔。空腔不形成在熔丝材料层的侧壁处，或者在与衬底相对的熔丝材料层的表面处。当熔丝材料层包括裂纹末端和较窄的中间区域时，可以在使用自对准蚀刻方法的同时在衬底和熔丝材料层之间形成空隙。空隙由支撑熔丝材料层的一对牺牲层基座分开。通过使用封装介电层将空隙封装以形成空腔。或者，当形成插入在基板和熔丝材料层之间的空隙时，可以使用块掩模。

7. 发明申请

US20080157268A1 Fuse Element Using Low-K Dielectric 审中-公开
标题翻译：使用低K电介质的保险丝元件
公开(公告)号：US20080157268A1
公开(公告)日：2008-07-03
申请号：US11618749
申请日：2006-12-30
申请人： Deok-kee Kim , Anil K. Chinthakindi , Kelly Malone , Son Van Nguyen , Byeongju Park
发明人： Deok-kee Kim , Anil K. Chinthakindi , Kelly Malone , Son Van Nguyen , Byeongju Park
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable structure such as a write once read many (WORM) or one time programmable read only memories (OTPROM) is disclosed herein. The structure includes a first conductor (such as copper) positioned within a substrate and a metal cap on the first conductor. A low-k dielectric is on the substrate and the metal cap. A tantalum nitride resistor is on the dielectric, and the resistor is positioned above the metal cap such that a programmable region of the dielectric is positioned between the resistor and the metal cap. The first conductor (including the metal cap), the programmable region of the dielectric, and the resistor form a metal-insulator-metal capacitor. Further, the programmable region of the dielectric is adapted to be permanently changed from heat produced by the resistor when a voltage difference is applied to the first and second ends of the resistor, respectively, through the first and second contacts. Thus, the capacitor comprises a first capacitance before the programmable region is permanently changed by the heat from the resistor and comprises a second capacitance after the programmable region is permanently changed by the heat from the resistor.
摘要翻译：这里公开了诸如一次写入一次读取（WORM）或一次可编程只读存储器（OTPROM）的可编程结构。该结构包括位于基板内的第一导体（例如铜）和第一导体上的金属盖。低k电介质位于基板和金属盖上。电介质上有一个氮化钽电阻器，电阻器位于金属帽的上方，使电介质的可编程区域位于电阻器和金属帽之间。第一导体（包括金属盖），电介质的可编程区域和电阻器形成金属 - 绝缘体 - 金属电容器。此外，电介质的可编程区域分别适用于当通过第一和第二触点将电压差分别施加到电阻器的第一和第二端时由电阻器产生的热量永久地改变。因此，电容器包括在可编程区域被来自电阻器的热量永久地变化之前的第一电容，并且在可编程区域被来自电阻器的热量永久地改变之后包括第二电容。

8. 发明申请

US20080079113A1 FUSE STRUCTURE INCLUDING CAVITY AND METHODS FOR FABRICATION THEREOF 失效
标题翻译：包括密封的保险丝结构及其制造方法
公开(公告)号：US20080079113A1
公开(公告)日：2008-04-03
申请号：US11538170
申请日：2006-10-03
申请人： Anil K. Chinthakindi , Deok-kee Kim , Chandrasekharan Kothandaraman
发明人： Anil K. Chinthakindi , Deok-kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure comprises a cavity interposed between a substrate and a fuse material layer. The cavity is not formed at a sidewall of the fuse material layer, or at a surface of the fuse material layer opposite the substrate. A void may be formed interposed between the substrate and the fuse material layer while using a self-aligned etching method, when the fuse material layer comprises lobed ends and a narrower middle region. The void is separated by a pair of sacrificial layer pedestals that support the fuse material layer. The void is encapsulated to form the cavity by using an encapsulating dielectric layer. Alternatively, a block mask may be used when forming the void interposed between the substrate and the fuse material layer.
摘要翻译：熔丝结构包括插入在基板和熔丝材料层之间的空腔。空腔不形成在熔丝材料层的侧壁处，或者在与衬底相对的熔丝材料层的表面处。当熔丝材料层包括裂纹末端和较窄的中间区域时，可以在使用自对准蚀刻方法的同时在衬底和熔丝材料层之间形成空隙。空隙由支撑熔丝材料层的一对牺牲层基座分开。通过使用封装介电层将空隙封装以形成空腔。或者，当形成插入在基板和熔丝材料层之间的空隙时，可以使用块掩模。

9. 发明授权

US07643268B2 High capacitance density vertical natural capacitors 失效
标题翻译：高电容密度垂直天然电容
公开(公告)号：US07643268B2
公开(公告)日：2010-01-05
申请号：US12194566
申请日：2008-08-20
申请人： Anil K. Chinthakindi
发明人： Anil K. Chinthakindi
IPC分类号： H01G4/228 , H01L27/108 , H01L29/94
CPC分类号： H01G4/228 , H01G4/30 , H01G4/33 , H01L23/5223 , H01L28/60 , H01L2924/0002 , Y10T29/417 , Y10T29/435 , H01L2924/00
摘要： Disclosed are embodiments of a capacitor with inter-digitated vertical plates and a method of forming the capacitor such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomplished during back end of the line processing by masking connecting points with nodes, by etching the dielectric material from between the vertical plates and by etching a sacrificial material from below the vertical plates. Etching of the dielectric material from between the plates forms air gaps and various techniques can be used to cause the plates to collapse in on these air gaps, once the sacrificial material is removed. Any remaining air gaps can be filled by depositing a second dielectric material (e.g., a high k dielectric), which will further increase the capacitance density and will encapsulate the capacitor in order to make the reduced distance between the vertical plates permanent.
摘要翻译：公开了具有数字化的垂直板的电容器的实施例以及形成电容器的方法，使得板之间的有效间隙距离减小。该间隙宽度减小显着增加了电容器的电容密度。通过用节点掩蔽连接点，通过从垂直板之间蚀刻电介质材料，并通过从垂直板下方蚀刻牺牲材料，在线加工的后端完成间隙宽度减小。一旦牺牲材料被去除，介质材料之间的介电材料的蚀刻形成气隙，并且可以使用各种技术来使板在这些气隙上塌陷。可以通过沉积第二电介质材料（例如，高k电介质）来填充任何剩余的气隙，这将进一步增加电容密度并封装电容器，以使得垂直板之间的距离减小。

10. 发明授权

US07608909B2 Suspended transmission line structures in back end of line processing 有权
标题翻译：线路处理后端的悬挂传输线结构
公开(公告)号：US07608909B2
公开(公告)日：2009-10-27
申请号：US11164765
申请日：2005-12-05
申请人： Anil K. Chinthakindi , Robert A. Groves , Youri V. Tretiakov , Kunal Vaed , Richard P. Volant
发明人： Anil K. Chinthakindi , Robert A. Groves , Youri V. Tretiakov , Kunal Vaed , Richard P. Volant
IPC分类号： H01L21/76
CPC分类号： H01P11/003 , H01L21/7682 , H01L21/76838 , H01L23/5222 , H01L23/5225 , H01L23/53238 , H01L2223/6622 , H01L2223/6627 , H01L2924/0002 , H01L2924/1903 , H01L2924/3011 , H01L2924/00
摘要： A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.
摘要翻译：用于形成用于半导体器件的传输线结构的方法包括在第一金属化层上形成层间电介质层，去除层间电介质层的一部分，并在通过去除部分的部分产生的一个或多个空隙内形成牺牲材料层间电介质层。信号传输线形成在层间电介质层上形成的第二金属化层，信号传输线设置在牺牲材料之上。包括在第二金属化水平内的电介质材料的一部分被去除以暴露牺牲材料，其中牺牲材料的一部分通过穿过信号传输线形成的多个访问孔而露出。去除牺牲材料，以在信号传输线下方产生气隙。

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