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1. 发明申请

US20130290640A1 BRANCH PREDICTION POWER REDUCTION 有权
标题翻译：分支预测功率降低
公开(公告)号：US20130290640A1
公开(公告)日：2013-10-31
申请号：US13458542
申请日：2012-04-27
申请人： Aneesh Aggarwal , Ross Segelken , Kevin Koschoreck , Paul Wasson
发明人： Aneesh Aggarwal , Ross Segelken , Kevin Koschoreck , Paul Wasson
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F1/32 , G06F1/3243 , G06F9/30058 , G06F9/38 , Y02D10/152
摘要： In one embodiment, a microprocessor is provided. The microprocessor includes instruction memory and a branch prediction unit. The branch prediction unit is configured to use information from the instruction memory to selectively power up the branch prediction unit from a powered-down state when fetched instruction data includes a branch instruction and maintain the branch prediction unit in the powered-down state when the fetched instruction data does not include a branch instruction in order to reduce power consumption of the microprocessor during instruction fetch operations.
摘要翻译：在一个实施例中，提供微处理器。微处理器包括指令存储器和分支预测单元。分支预测单元被配置为当获取的指令数据包括分支指令时，使用来自指令存储器的信息来选择性地从掉电状态向上行分支预测单元加电，并且当所提取的指令数据包含分支指令时，将分支预测单元维持在断电状态指令数据不包括分支指令，以便在指令获取操作期间减少微处理器的功耗。

2. 发明授权

US09552032B2 Branch prediction power reduction 有权
标题翻译：分支预测功率降低
公开(公告)号：US09552032B2
公开(公告)日：2017-01-24
申请号：US13458542
申请日：2012-04-27
申请人： Aneesh Aggarwal , Ross Segelken , Kevin Koschoreck , Paul Wasson
发明人： Aneesh Aggarwal , Ross Segelken , Kevin Koschoreck , Paul Wasson
IPC分类号： G06F9/38 , G06F1/32 , G06F9/30
CPC分类号： G06F1/32 , G06F1/3243 , G06F9/30058 , G06F9/38 , Y02D10/152
摘要： In one embodiment, a microprocessor is provided. The microprocessor includes instruction memory and a branch prediction unit. The branch prediction unit is configured to use information from the instruction memory to selectively power up the branch prediction unit from a powered-down state when fetched instruction data includes a branch instruction and maintain the branch prediction unit in the powered-down state when the fetched instruction data does not include a branch instruction in order to reduce power consumption of the microprocessor during instruction fetch operations.
摘要翻译：在一个实施例中，提供微处理器。微处理器包括指令存储器和分支预测单元。分支预测单元被配置为当获取的指令数据包括分支指令时，使用来自指令存储器的信息来选择性地从掉电状态向上行分支预测单元加电，并且当所提取的指令数据包含分支指令时，将分支预测单元维持在断电状态指令数据不包括分支指令，以便在指令获取操作期间减少微处理器的功耗。

3. 发明申请

US20130290676A1 BRANCH PREDICTION POWER REDUCTION 有权
标题翻译：分支预测功率降低
公开(公告)号：US20130290676A1
公开(公告)日：2013-10-31
申请号：US13458513
申请日：2012-04-27
申请人： Aneesh Aggarwal , Ross Segelken , Paul Wasson
发明人： Aneesh Aggarwal , Ross Segelken , Paul Wasson
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F1/3243 , G06F9/30058 , Y02D10/152
摘要： In one embodiment, a microprocessor is provided. The microprocessor includes a branch prediction unit. The branch prediction unit is configured to track the presence of branches in instruction data that is fetched from an instruction memory after a redirection at a target of a predicted taken branch. The branch prediction unit is selectively powered up from a powered-down state when the fetched instruction data includes a branch instruction and is maintained in the powered-down state when the fetched instruction data does not include an instruction branch in order to reduce power consumption of the microprocessor during instruction fetch operations.
摘要翻译：在一个实施例中，提供微处理器。微处理器包括分支预测单元。分支预测单元被配置为跟踪在预测的分支的目标上的重定向之后从指令存储器取出的指令数据中的分支的存在。当获取的指令数据包括分支指令时，分支预测单元从掉电状态选择性地加电，并且当所提取的指令数据不包括指令分支时，分支预测单元被维持在掉电状态，以便降低功耗指令提取操作期间的微处理器。

4. 发明授权

US09547358B2 Branch prediction power reduction 有权
标题翻译：分支预测功率降低
公开(公告)号：US09547358B2
公开(公告)日：2017-01-17
申请号：US13458513
申请日：2012-04-27
申请人： Aneesh Aggarwal , Ross Segelken , Paul Wasson
发明人： Aneesh Aggarwal , Ross Segelken , Paul Wasson
IPC分类号： G06F9/30 , G06F1/32
CPC分类号： G06F1/3243 , G06F9/30058 , Y02D10/152
摘要： In one embodiment, a microprocessor is provided. The microprocessor includes a branch prediction unit. The branch prediction unit is configured to track the presence of branches in instruction data that is fetched from an instruction memory after a redirection at a target of a predicted taken branch. The branch prediction unit is selectively powered up from a powered-down state when the fetched instruction data includes a branch instruction and is maintained in the powered-down state when the fetched instruction data does not include an instruction branch in order to reduce power consumption of the microprocessor during instruction fetch operations.
摘要翻译：在一个实施例中，提供微处理器。微处理器包括分支预测单元。分支预测单元被配置为跟踪在预测的分支的目标上的重定向之后从指令存储器取出的指令数据中的分支的存在。当获取的指令数据包括分支指令时，分支预测单元从掉电状态选择性地加电，并且当所提取的指令数据不包括指令分支时，分支预测单元被维持在掉电状态，以便降低功耗指令提取操作期间的微处理器。

5. 发明授权

US5970474A Registry information system for shoppers 失效
标题翻译：购物者注册表信息系统
公开(公告)号：US5970474A
公开(公告)日：1999-10-19
申请号：US842334
申请日：1997-04-24
申请人： Michael LeRoy , Paul Wasson , James Brabson , Ron Trainer
发明人： Michael LeRoy , Paul Wasson , James Brabson , Ron Trainer
IPC分类号： G06Q20/20 , G06Q30/06 , G06F17/60
CPC分类号： G06Q30/06 , G06Q20/208 , G06Q30/0623 , G06Q30/0633 , G06Q30/0641
摘要： A product information system for selecting, monitoring and purchasing of products in a retail establishment includes a product selection device, a data processor, a registry retrieval device, a point-of-sale data input device, and a host computer. The product selection device identifies desired items selected by a registrant and routes the desired items to a registry database on a host computer. The data processor is adapted to communicate with the product selection device to thereby collect the desired items selected by the registrant and route the desired items to the host computer. The registry retrieval device is configured to retrieve updated registry data from the host computer in response to a request from a purchasing customer. The retrieval device has an output unit for displaying an updated list of items in the registry database. The point-of-sale data input device identifies desired items which have been purchased by a customer for routing to the host computer. The host computer has a storage unit for maintaining the registry database and a data processor for processing selection and purchasing transactions. Thus, desired items consecutively selected by the registrant are added to the registry database to create a registry list, and desired items purchased by the customer are associated with the registry database to create an updated list reflecting the purchase of said desired items.
摘要翻译：用于在零售店中选择，监视和购买产品的产品信息系统包括产品选择装置，数据处理器，注册表检索装置，销售点数据输入装置和主计算机。产品选择设备识别由注册人选择的期望项目，并将所需项目路由到主计算机上的注册数据库。数据处理器适于与产品选择设备进行通信，从而收集由注册者选择的期望项目并将所需项目路由到主计算机。注册表检索设备被配置为响应于来自购买客户的请求从主计算机检索更新的注册表数据。检索装置具有用于在注册表数据库中显示更新的项目列表的输出单元。销售点数据输入装置识别客户购买的用于路由到主计算机的所需项目。主机具有用于维护注册数据库的存储单元和用于处理选择和购买交易的数据处理器。因此，由注册者连续选择的期望项目被添加到注册表数据库以创建注册表列表，并且由客户购买的期望项目与注册数据库相关联，以创建反映购买所述期望项目的更新列表。

6. 发明申请

US20070180334A1 MULTI-FREQUENCY DEBUG NETWORK FOR A MULTIPROCESSOR ARRAY 有权
标题翻译：多频调频阵列的多频调制网络
公开(公告)号：US20070180334A1
公开(公告)日：2007-08-02
申请号：US11676206
申请日：2007-02-16
申请人： Anthony Jones , Paul Wasson , Edmund White
发明人： Anthony Jones , Paul Wasson , Edmund White
IPC分类号： G06F11/00
CPC分类号： G06F11/362
摘要： A debug network on a multiprocessor array having multiple clock domains includes a backbone communication channel which communicates with information nodes on the channel. The information nodes store and access information about an attached processor. The nodes are also coupled to registers within the attached processor, which operate at the speed of the processor. A master controller solicits information from the information nodes by sending messages along the backbone. If a message requires interaction with a processor register, the node performs the action by synchronizing to the local processor clock.
摘要翻译：具有多个时钟域的多处理器阵列上的调试网络包括与信道上的信息节点进行通信的骨干通信信道。信息节点存储和访问有关附加处理器的信息。节点还耦合到附接处理器内的寄存器，其以处理器的速度工作。主控制器通过沿主干发送消息从信息节点请求信息。如果消息需要与处理器寄存器进行交互，则节点通过与本地处理器时钟同步来执行操作。

7. 发明申请

US20070025382A1 System of virtual data channels in an integrated circuit 有权
标题翻译：集成电路中的虚拟数据通道系统
公开(公告)号：US20070025382A1
公开(公告)日：2007-02-01
申请号：US11340957
申请日：2006-01-27
申请人： Anthony Jones , Paul Wasson , Michael Butts
发明人： Anthony Jones , Paul Wasson , Michael Butts
IPC分类号： H04L12/28
CPC分类号： H04L12/40019
摘要： This disclosure relates to a system of communicating, data within an integrated circuit. Multiple components, or channels, can share common physical communication lines between elements within the system. In some aspect, only one component can access the physical lines at a given time and a selection device chooses which component is active on the physical lines and makes the appropriate connection to the lines. The selection and connection can be completed without requiring or reporting information to the components, and is thus transparent.
摘要翻译：本公开涉及在集成电路内传送数据的系统。多个组件或通道可以在系统内的元件之间共享通用的物理通信线路。在某些方面，只有一个组件可以在给定时间访问物理线路，并且选择设备选择物理线路上的哪个组件是活动的，并且对线路进行适当的连接。可以完成选择和连接，而不需要或向组件报告信息，因此是透明的。

8. 发明申请

US20070124565A1 RECONFIGURABLE PROCESSING ARRAY HAVING HIERARCHICAL COMMUNICATION NETWORK 审中-公开
标题翻译：具有分层通信网络的可重构处理阵列
公开(公告)号：US20070124565A1
公开(公告)日：2007-05-31
申请号：US11557478
申请日：2006-11-07
申请人： Anthony Jones , Paul Wasson , Michael Butts
发明人： Anthony Jones , Paul Wasson , Michael Butts
IPC分类号： G06F9/40 , G06F15/00
CPC分类号： G06F15/17337
摘要： A processor includes multiple compute units and memory units arranged in groups of abutted tiles. Multiple tiles are arranged together along with input/output interfaces to form a processor system that can be configured to perform many different operations. A hierarchical communication network efficiently connects components within the tiles and between multiple tiles.
摘要翻译：处理器包括多个计算单元和以对接的瓦片组成排列的存储器单元。多个瓦片与输入/输出接口一起布置在一起以形成可配置成执行许多不同操作的处理器系统。分级通信网络有效地连接瓦片内的组件和多个瓦片之间的组件。

9. 发明申请

US20070180323A1 INTERACTIVE DEBUG SYSTEM FOR MULTIPROCESSOR ARRAY 有权
标题翻译：多处理器阵列的互动调试系统
公开(公告)号：US20070180323A1
公开(公告)日：2007-08-02
申请号：US11673986
申请日：2007-02-12
申请人： Anthony Jones , Paul Wasson , Edmund White
发明人： Anthony Jones , Paul Wasson , Edmund White
IPC分类号： G06F11/00
CPC分类号： G06F11/362 , G06F17/5045
摘要： A debug network on a multiprocessor array includes communication channels, a master controller, and one or more individual debug units in communication with one or more of the processors. The master controller soilcits information from the debug units by sending messages along the communication channels. The debug units can control some aspects of the processors, and can simply report on other aspects. By using commands to invoke processor action, then accessing the result, interactive debugging of a multiprocessor array is possible.
摘要翻译：多处理器阵列上的调试网络包括与一个或多个处理器通信的通信信道，主控制器和一个或多个单独的调试单元。主控制器通过沿着通信信道发送消息来弄脏来自调试单元的信息。调试单元可以控制处理器的某些方面，并且可以简单地报告其他方面。通过使用命令调用处理器操作，然后访问结果，可以进行多处理器阵列的交互式调试。

10. 发明申请

US20070169022A1 PROCESSOR HAVING MULTIPLE INSTRUCTION SOURCES AND EXECUTION MODES 审中-公开
标题翻译：具有多种指令来源和执行模式的处理程序
公开(公告)号：US20070169022A1
公开(公告)日：2007-07-19
申请号：US11672450
申请日：2007-02-07
申请人： Anthony Jones , Paul Wasson , Michael Butts
发明人： Anthony Jones , Paul Wasson , Michael Butts
IPC分类号： G06F9/45
CPC分类号： G06F9/3802 , G06F9/30054 , G06F9/30076 , G06F9/30181 , G06F9/30189 , G06F9/3877 , G06F9/3885 , G06F9/3891 , G06F15/7842
摘要： A processor includes the standard mode of executing instructions from stored memory as well as a mode of executing from a separate instruction source. A programmable selector determines the source, and may be automatically programmed dependent on particular instructions. Streaming instructions from outside the processor provides an ability to have infinite program space. Further, booting processors in such an execution mode allows systems to be configured from external sources.
摘要翻译：处理器包括从存储的存储器执行指令的标准模式以及从单独的指令源执行的模式。可编程选择器确定源，并且可以根据特定指令自动编程。来自处理器外部的流指令提供了无限程序空间的能力。此外，以这种执行模式启动处理器允许从外部源配置系统。

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