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1. 发明授权

US06928494B1 Method and apparatus for timing-dependant transfers using FIFOs 失效
标题翻译：使用FIFO进行定时相关传输的方法和装置
公开(公告)号：US06928494B1
公开(公告)日：2005-08-09
申请号：US09538386
申请日：2000-03-29
申请人： Andrew M. Volk , Michael W. Williams , David J. McDonnell
发明人： Andrew M. Volk , Michael W. Williams , David J. McDonnell
IPC分类号： G11C7/10 , G06F3/00
CPC分类号： G11C7/10
摘要： A method and apparatus for communicating commands and/or data between two different time domains. In one embodiment, multiple memory commands are placed into one or more FIFOs in a manner that specifies the delays that must take place between execution of the different commands. Along with the commands, delay information is placed into the FIFOs, specifying the number of clock cycles, or other form of time delay, that must elapse between execution of a command and execution of a subsequent command. This delay information is used to delay the execution of the subsequent command for the specified time period, while minimizing or eliminating any excess delays. Cue information can also be placed into the FIFOs with the commands to specify which commands must wait for other commands before beginning execution. The delay and cue information is determined and created in the time domain that initiates the transfers. The delays and cueing are executed in the other time domain. Although the different commands may be delivered through different FIFOs and can therefore have unpredictable arrival times with respect to each other, the delay and cueing information maintains the proper execution order and timing between the commands. Interactive control logic at the output of each FIFO uses the timing data to maintain execution in the proper order and with the proper inter-command delays.
摘要翻译：一种用于在两个不同时域之间传送命令和/或数据的方法和装置。在一个实施例中，多个存储器命令以指定在不同命令的执行之间必须发生的延迟的方式被放置到一个或多个FIFO中。与命令一起，将延迟信息放入FIFO中，指定执行命令和执行后续命令之间必须经过的时钟周期数量或其他形式的时间延迟。该延迟信息用于在指定的时间段内延迟后续命令的执行，同时最小化或消除任何多余的延迟。提示信息也可以放在FIFO中，其命令用于指定哪些命令在开始执行之前必须等待其他命令。在启动传输的时域中确定和创建延迟和提示信息。延迟和提示在其他时间域执行。虽然不同的命令可以通过不同的FIFO传递，并且因此可以相对于彼此具有不可预测的到达时间，但延迟和提示信息保持命令之间的正确的执行顺序和定时。每个FIFO的输出端的交互控制逻辑使用定时数据来维持正确顺序的执行和适当的指令间延迟。

2. 发明授权

US06915399B1 Cross-clock domain data transfer method and apparatus 失效
标题翻译：跨时钟域数据传输方法和装置
公开(公告)号：US06915399B1
公开(公告)日：2005-07-05
申请号：US09524942
申请日：2000-03-14
申请人： David J. McDonnell , Andrew M. Volk , Michael W. Williams
发明人： David J. McDonnell , Andrew M. Volk , Michael W. Williams
IPC分类号： G06F1/04 , G06F12/00 , G06F13/00 , H04L12/403 , H04L12/54
CPC分类号： G06F5/06 , G06F13/1689 , G06F2205/061
摘要： An apparatus and method for transferring units of information between clock domains. A respective set of N units of information is loaded from an output circuit in a first clock domain into a storage circuit in a second clock domain during each cycle of the first clock domain. Each set of N units is selected by the output circuit to include (1) units of information that have previously loaded into the storage circuit and that will not be output from the storage output from the storage circuit prior to the storage circuit being loaded with a subsequent set of N units of information, and (2) a complement number of units of information that have not previously been loaded into the storage circuit.
摘要翻译：一种用于在时钟域之间传送信息单元的装置和方法。在第一时钟域的每个周期期间，将相应的N个信息单元从第一时钟域中的输出电路加载到第二时钟域中的存储电路中。每一组N个单元由输出电路选择，以包括（1）先前已经加载到存储电路中的信息单元，并且在存储电路被加载之前不会从存储电路的存储输出输出随后的一组N个信息，以及（2）补充数量的先前未被加载到存储电路中的信息单元。

3. 发明授权

US6128749A Cross-clock domain data transfer method and apparatus 有权
标题翻译：跨时钟域数据传输方法和装置
公开(公告)号：US6128749A
公开(公告)日：2000-10-03
申请号：US186046
申请日：1998-11-03
申请人： David J. McDonnell , Andrew M. Volk , Michael W. Williams
发明人： David J. McDonnell , Andrew M. Volk , Michael W. Williams
IPC分类号： G06F1/04 , G06F12/00 , G06F13/00 , H04L12/403 , H04L12/54
CPC分类号： G06F5/06 , G06F13/1689 , G06F2205/061
摘要： An apparatus and method for transferring units of information between clock domains. A respective set of N units of information is loaded from an output circuit in a first clock domain into a storage circuit in a second clock domain during each cycle of the first clock domain. Each set of N units is selected by the output circuit to include (1) units of information that have previously been loaded into the storage circuit and that will not be output from the storage circuit prior to the storage circuit being loaded with a subsequent set of N units of information, and (2) a complement number of units of information that have not previously been loaded into the storage circuit.
摘要翻译：一种用于在时钟域之间传送信息单元的装置和方法。在第一时钟域的每个周期期间，将相应的N个信息单元从第一时钟域中的输出电路加载到第二时钟域中的存储电路中。每一组N个单元由输出电路选择，包括（1）先前已经被加载到存储电路中的信息单元，并且在存储电路装载下一组 N个信息单元，以及（2）尚未加载到存储电路中的补充信息单元。

4. 发明授权

US06771669B1 Method and apparatus for remote memory clock synchronization for optimized leadoff performance 有权
标题翻译：用于远程存储器时钟同步的方法和装置，用于优化引导线性能
公开(公告)号：US06771669B1
公开(公告)日：2004-08-03
申请号：US09475458
申请日：1999-12-30
申请人： David J. McDonnell , Himanshu Sinha
发明人： David J. McDonnell , Himanshu Sinha
IPC分类号： H04J306
CPC分类号： H04L7/10 , H04L7/0037
摘要： A method and apparatus for synchronizing a synchronizing clock is disclosed for use in synchronizing a high-speed memory bus with a second, heritage memory bus. This method and apparatus includes generating an initial synchronizing clock from a reference clock of the high-speed memory bus. It then includes receiving a synchronizing packet on the high-speed memory bus utilizing the initial synchronizing clock. Finally, it includes delaying a clock transition of the initial synchronizing clock in response to the received data of the synchronizing packet.
摘要翻译：公开了用于使同步时钟同步的方法和装置，用于使高速存储器总线与第二遗留存储器总线同步。该方法和装置包括从高速存储器总线的参考时钟产生初始同步时钟。然后，它包括利用初始同步时钟在高速存储器总线上接收同步分组。最后，它包括响应于同步分组的接收数据延迟初始同步时钟的时钟转换。

5. 发明授权

US06470238B1 Method and apparatus to control device temperature 有权
标题翻译：控制装置温度的方法和装置
公开(公告)号：US06470238B1
公开(公告)日：2002-10-22
申请号：US09335101
申请日：1999-06-17
申请人： Puthiya K. Nizar , David J. McDonnell , Brian K. Langendorf , Michael G. LaTondre , Jeff L. Rabe , Tom A. Sutera , Zohar Bogin , Vincent E. VonBokern
发明人： Puthiya K. Nizar , David J. McDonnell , Brian K. Langendorf , Michael G. LaTondre , Jeff L. Rabe , Tom A. Sutera , Zohar Bogin , Vincent E. VonBokern
IPC分类号： G05D2300
CPC分类号： G06F13/1668
摘要： A method for controlling device temperature. The method involves determining access rate to a component, comparing the access rate with a predetermined threshold modified by a weighted value and controlling the temperature of the component through corrective action.
摘要翻译：一种控制装置温度的方法。该方法涉及确定对组件的访问速率，将访问速率与由加权值修改的预定阈值进行比较，并通过纠正措施控制组件的温度。

6. 发明授权

US06940816B2 Method and apparatus for a slot-based memory controller 失效
标题翻译：用于基于槽的存储器控制器的方法和装置
公开(公告)号：US06940816B2
公开(公告)日：2005-09-06
申请号：US09752371
申请日：2000-12-29
申请人： David J. McDonnell
发明人： David J. McDonnell
IPC分类号： H04L12/56 , H04L29/06 , G01R31/08
CPC分类号： H04L49/901 , H04L29/06 , H04L49/90
摘要： A memory controller is disclosed. The memory controller includes a slot-based controller adaptable to launch a packet that straddles a first fixed packet slot and a second fixed packet slot.
摘要翻译：公开了一种存储器控制器。存储器控制器包括适于发射跨越第一固定分组时隙和第二固定分组时隙的分组的基于时隙的控制器。

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