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1. 发明申请

US20050101072A1 Transistor structure with thick recessed source/drain structures and fabrication process of same 失效
公开(公告)号：US20050101072A1
公开(公告)日：2005-05-12
申请号：US11007843
申请日：2004-12-09
申请人： Andres Bryant , Mark Jaffe
发明人： Andres Bryant , Mark Jaffe
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/786 , H01L21/00 , H01L21/8238
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/41733 , H01L29/42384 , H01L29/66772 , H01L29/66795
摘要： An improved transistor structure that decreases source/drain (S/D) resistance without increasing gate-to-S/D capacitance, thereby increasing device operation. S/D structures are formed into recesses formed on a semiconductor wafer through a semiconductor layer and a first layer of a buried insulator having at least two layers. A body is formed from the semiconductor layer situated between the recesses, and the body comprises a top body surface and a bottom body surface that define a body thickness. Top portions of the S/D structures are within and abut the body thickness. An improved method for forming the improved transistor structure is also described and comprises: forming recesses through a semiconductor layer and a first layer of a buried insulator so that a body is situated between the recesses; and forming S/D structures into the recesses so that top portions of the S/D structures are within and abut a body thickness.

2. 发明申请

US20060226456A1 PIXEL SENSOR CELL HAVING REDUCED PINNING LAYER BARRIER POTENTIAL AND METHOD THEREOF 有权
标题翻译：具有减少的钉扎层障碍物的像素传感器电池及其方法
公开(公告)号：US20060226456A1
公开(公告)日：2006-10-12
申请号：US10907570
申请日：2005-04-06
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
IPC分类号： H01L31/113
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L31/0352
摘要： A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.
摘要翻译：像素传感器单元结构及其制造方法。像素单元包括与传输栅极结构的第一侧相邻形成的用于耦合收集阱区和沟道区的掺杂层。减少了由钉扎层引起的对电荷转移的电势障碍干扰。

3. 发明申请

US20070029581A1 PIXEL SENSOR CELL FOR COLLECTING ELECTRONS AND HOLES 失效
标题翻译：用于收集电子和孔的像素传感器单元
公开(公告)号：US20070029581A1
公开(公告)日：2007-02-08
申请号：US11161535
申请日：2005-08-08
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Mark Jaffe , Jeffrey Johnson , Alain Loiseau
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Mark Jaffe , Jeffrey Johnson , Alain Loiseau
IPC分类号： H01L27/148
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14689 , H01L31/035281
摘要： The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.
摘要翻译：本发明是像素传感器单元及其制造方法。像素传感器单元对于给定的光量大约使可用信号加倍。本发明的器件利用通过在像素传感器单元电路中照射光子而产生的空穴。具有降低的复杂度的像素传感器单元包括形成在基板的表面下面的n型收集阱区域，用于收集由电子辐射照射在像素传感器单元上产生的电子以及形成在基板表面下方的p型收集阱区域用于收集由撞击光子产生的孔。具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小的第一输入和第二输入的信号。

4. 发明申请

US20070296006A1 STRUCTURE FOR PIXEL SENSOR CELL THAT COLLECTS ELECTRONS AND HOLES 失效
标题翻译：用于收集电子和孔的像素传感器单元的结构
公开(公告)号：US20070296006A1
公开(公告)日：2007-12-27
申请号：US11850776
申请日：2007-09-06
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Mark Jaffe , Jeffrey Johnson , Alain Loiseau
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Mark Jaffe , Jeffrey Johnson , Alain Loiseau
IPC分类号： H01L31/00
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14689 , H01L31/035281 , H01L31/1037
摘要： The present invention relates to a design structure for a pixel sensor cell. The pixel sensor cell approximately doubles the available signal for a given quanta of light. A design structure for a pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.
摘要翻译：本发明涉及一种像素传感器单元的设计结构。像素传感器单元对于给定的光量大约使可用信号加倍。具有降低的复杂度的像素传感器单元的设计结构包括形成在基板的表面下面的n型收集阱区域，用于收集电子辐射产生的电子撞击在像素传感器单元上，以及p型收集阱区域用于收集由撞击光子产生的孔的基板的表面。具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小的第一输入和第二输入的信号。

5. 发明申请

US20070145438A1 PIXEL SENSOR CELL HAVING REDUCED PINNING LAYER BARRIER POTENTIAL AND METHOD THEREOF 有权
标题翻译：具有减少的钉扎层障碍物的像素传感器电池及其方法
公开(公告)号：US20070145438A1
公开(公告)日：2007-06-28
申请号：US11681454
申请日：2007-03-02
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
IPC分类号： H01L31/113
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L31/0352
摘要： A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.
摘要翻译：像素传感器单元结构及其制造方法。像素单元包括与传输栅极结构的第一侧相邻形成的用于耦合收集阱区和沟道区的掺杂层。减少了由钉扎层引起的对电荷转移的电势障碍干扰。

6. 发明申请

US20050272195A1 Integrated circuit having pairs of parallel complementary finfets 失效
标题翻译：具有并联互补鳍对的集成电路
公开(公告)号：US20050272195A1
公开(公告)日：2005-12-08
申请号：US11186748
申请日：2005-07-21
申请人： Andres Bryant , William Clark , David Fried , Mark Jaffe , Edward Nowak , John Pekarik , Christopher Putnam
发明人： Andres Bryant , William Clark , David Fried , Mark Jaffe , Edward Nowak , John Pekarik , Christopher Putnam
IPC分类号： H01L21/308 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/8232
CPC分类号： H01L21/84 , H01L21/3086 , H01L21/3088 , H01L21/823821 , H01L27/1203 , H01L29/66795 , H01L29/785 , Y10S438/947
摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.
摘要翻译：公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。第一鳍片和第二鳍片具有大致相同的宽度。

7. 发明申请

US20050001273A1 INTEGRATED CIRCUIT HAVING PAIRS OF PARALLEL COMPLEMENTARY FINFETS 有权
标题翻译：具有并联补偿器件对的集成电路
公开(公告)号：US20050001273A1
公开(公告)日：2005-01-06
申请号：US10604206
申请日：2003-07-01
申请人： Andres Bryant , William Clark , David Fried , Mark Jaffe , Edward Nowak , John Pekarik , Christopher Putnam
发明人： Andres Bryant , William Clark , David Fried , Mark Jaffe , Edward Nowak , John Pekarik , Christopher Putnam
IPC分类号： H01L21/308 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L33/00
CPC分类号： H01L21/84 , H01L21/3086 , H01L21/3088 , H01L21/823821 , H01L27/1203 , H01L29/66795 , H01L29/785 , Y10S438/947
摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.
摘要翻译：公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。第一鳍片和第二鳍片具有大致相同的宽度。

8. 发明授权

US09768304B2 Method of fabricating a FINFET having a gate structure disposed at least partially at a bend region of the semiconductor fin 有权
公开(公告)号：US09768304B2
公开(公告)日：2017-09-19
申请号：US13492108
申请日：2012-06-08
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/20 , H01L29/78 , H01L21/8238 , H01L27/12 , H01L29/10 , H01L21/3115 , H01L21/762 , H01L29/66
CPC分类号： H01L29/785 , H01L21/31155 , H01L21/76283 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1203 , H01L29/1037 , H01L29/66621 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.

9. 发明授权

US08941180B2 Integrated circuit structure incorporating one or more asymmetric field effect transistors as power gates for an electronic circuit with stacked symmetric field effect transistors 有权
标题翻译：集成电路结构，其包括一个或多个不对称场效应晶体管作为具有堆叠对称场效应晶体管的电子电路的功率门
公开(公告)号：US08941180B2
公开(公告)日：2015-01-27
申请号：US13044872
申请日：2011-03-10
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L27/02 , H01L27/12 , H01L21/8234 , H01L29/786 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L29/78624
摘要： Disclosed is an integrated circuit having an asymmetric FET as a power gate for an electronic circuit, which has at least two stacked symmetric field effect transistors. The asymmetric FET has an asymmetric halo configuration (i.e., a single source-side halo or a source-side halo with a higher dopant concentration than a drain-side halo) and an asymmetric source/drain extension configuration (i.e., the source extension can be overlapped to a greater extent by the gate structure than the drain extension and/or the source extension can have a higher dopant concentration than the drain extension). As a result, the asymmetric FET has a low off current. In operation, the asymmetric FET is turned off when the electronic circuit is placed in a standby state and, due to the low off current (Ioff), effectively reduces standby leakage current from the electronic circuit. Additionally, avoiding the use of stacked asymmetric field effect transistors within the electronic circuit itself prevents performance degradation due to reduced linear drain current (Idlin).
摘要翻译：公开了具有不对称FET作为电子电路的功率门的集成电路，其具有至少两个堆叠的对称场效应晶体管。非对称FET具有不对称的卤素配置（即，具有比漏极侧卤素更高的掺杂剂浓度的单个源极卤素或源极卤素）和非对称源极/漏极延伸配置（即，源极延伸可以通过栅极结构比漏极延伸更大程度地重叠和/或源极延伸可以具有比漏极延伸更高的掺杂剂浓度）。结果，不对称FET具有低截止电流。在操作中，当电子电路处于待机状态时，不对称FET被关闭，并且由于低关断电流（Ioff），有效地减少了来自电子电路的待机漏电流。另外，避免使用电子电路内的层叠的非对称场效应晶体管本身可以防止由于线性漏极电流（Idlin）的降低导致的性能劣化。

10. 发明授权

US08900954B2 Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening 有权
标题翻译：毯子短通道卷起植入物，具有通过图案化开口的非角度长通道补偿植入物
公开(公告)号：US08900954B2
公开(公告)日：2014-12-02
申请号：US13289051
申请日：2011-11-04
申请人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/772 , H01L21/336 , H01L21/28 , H01L29/66 , H01L29/10 , H01L21/265
CPC分类号： H01L29/1041 , H01L21/2652 , H01L21/26586 , H01L21/28026 , H01L29/0847 , H01L29/1045 , H01L29/36 , H01L29/66537 , H01L29/66583 , H01L29/6659 , H01L29/78
摘要： A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.
摘要翻译：一种形成将衬底植入衬底的结构的方法，在衬底上图案掩模（具有暴露衬底的沟道区的至少一个开口），并在掩模上形成共形电介质层并使开口。保形介电层覆盖衬底的沟道区。该方法还在保形电介质层上形成共形栅极金属层，通过共形栅极金属层和共形绝缘层将补偿注入植入衬底的沟道区，并在共形栅极金属层上形成栅极导体。此外，该方法去除掩模以在衬底上留下栅极堆叠，在栅极堆叠上形成侧壁间隔物，然后在衬底中部分地在侧壁间隔物下方形成源极/漏极区域。

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