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    • 3. 发明授权
    • Method and integrated circuit for increasing the immunity to interference
    • 用于增加抗干扰性的方法和集成电路
    • US08578258B2
    • 2013-11-05
    • US10590087
    • 2005-02-17
    • Wolfgang FeyMicha HeinzAdrian TraskovFrank Michel
    • Wolfgang FeyMicha HeinzAdrian TraskovFrank Michel
    • G06F11/00
    • G06F11/0772G06F11/0724G06F11/0736G06F11/0739G06F11/1645G06F11/2215
    • Disclosed is a method of improving the immunity to interference of an integrated circuit (16) having error signals transferred between a microprocessor chip or multiple processor μC (1) and an additional component (2). For the transfer, a minimum pulse length that is independent of the clock frequency of the microprocessor or the microprocessors is defined, starting from which a signal on an error line having a defined pulse length is interpreted as an error. Also disclosed is an integrated circuit, which is designed so that the above method is implemented. The circuit has a microprocessor chip or multiple processor microcontroller (1) or microprocessor module and an additional component (2) having separately arranged power elements. The circuit also has pulse extending devices and/or signal delaying devices for the output of error pulses (6, 6′) one after the other through at least one error line (3, 4).
    • 公开了一种提高在微处理器芯片或多处理器muC(1)与附加部件(2)之间传送的误差信号的集成电路(16)的抗干扰性的方法。 对于传输,定义了与微处理器或微处理器的时钟频率无关的最小脉冲长度,从而将具有定义的脉冲长度的误差线上的信号从该脉冲长度解释为误差。 还公开了一种集成电路,其被设计为实现上述方法。 该电路具有微处理器芯片或多处理器微控制器(1)或微处理器模块以及具有单独布置的功率元件的附加组件(2)。 电路还具有脉冲延伸装置和/或信号延迟装置,用于通过至少一个误差线(3,4)一个接一个地输出误差脉冲(6,6')。
    • 4. 发明授权
    • Microprocessor system for controlling or regulating at least partly safety-critical processes
    • 用于控制或调节至少部分安全关键过程的微处理器系统
    • US09529681B2
    • 2016-12-27
    • US12063458
    • 2006-08-02
    • Wolfgang FeyAndreas KirschbaumAdrian Traskov
    • Wolfgang FeyAndreas KirschbaumAdrian Traskov
    • G06F11/00G06F11/16G06F11/10
    • G06F11/1641G06F11/1048
    • A microprocessor system (50) for controlling or regulating at least partly safety-critical processes, comprising two central processing units (1, 2) integrated in a chip housing, a first and a second bus system, at least one full memory (7) on the first bus system, at least one test data store (51) on the second bus system, which has a reduced store coverage compared to the full memory on the first bus system and in which test data are stored which are connected to data of the memory (7) on the first bus system, and the bus systems comprise comparison and/or driver components which allow the data interchange and/or comparison of data between the two bus systems, and a hardware test data generator (4) is arranged at least on the second bus system, in which case at least part of the full memory on the first bus is additionally backed up using another test data store (5) and test data on the first bus. The invention further relates to the use of the above microprocessor system in motor vehicle controllers.
    • 一种用于控制或调节至少部分安全关键过程的微处理器系统(50),包括集成在芯片壳体中的两个中央处理单元(1,2),第一和第二总线系统,至少一个完整存储器(7) 在第一总线系统上,在第二总线系统上的至少一个测试数据存储器(51),其与第一总线系统上的完整存储器相比具有减小的存储覆盖率,并且其中存储测试数据,其连接到 第一总线系统上的存储器(7),以及总线系统包括允许数据交换和/或比较两个总线系统之间的数据的比较和/或驱动器组件,并且硬件测试数据发生器(4)被布置 至少在第二总线系统上,在这种情况下,使用另一测试数据存储器(5)和第一总线上的测试数据另外备份第一总线上的至少部分全存储器。 本发明还涉及上述微处理器系统在机动车控制器中的应用。
    • 5. 发明授权
    • Microprocessor system for controlling at least partly safety-critical processes
    • 用于控制至少部分安全关键过程的微处理器系统
    • US08219860B2
    • 2012-07-10
    • US12063467
    • 2006-08-02
    • Wolfgang FeyAndreas KirschbaumAdrian Traskov
    • Wolfgang FeyAndreas KirschbaumAdrian Traskov
    • G01R31/28
    • G06F11/1048G06F11/1641G06F11/1654
    • The invention relates to a microprocessor system (60) for controlling and/or regulating at least partly security-critical processes, which system comprises two central processing units (1, 2) integrated into a chip housing, a first and a second bus system, at least one complete memory (7) on the first bus system, and check data in one or more check data memories, said data being related to data of the memory in the first bus system. The check data memory is smaller than the complete memory. The bus systems comprise comparative and/or driver components which facilitate data exchange and/or comparison of data between the two bus systems. The one or more check data memories are arranged on the first bus system. On the second bus system, neither a check data memory nor a memory safeguarding data of the memory on the first bus is used. The invention also relates to the use of the inventive microprocessor system in automotive control devices.
    • 本发明涉及一种用于控制和/或调节至少部分安全关键性过程的微处理器系统(60),该系统包括集成在芯片壳体中的两个中央处理单元(1,2),第一和第二总线系统, 在第一总线系统上的至少一个完整存储器(7),以及检查一个或多个检查数据存储器中的数据,所述数据与第一总线系统中的存储器的数据有关。 检查数据存储器小于完整存储器。 总线系统包括促进两个总线系统之间的数据交换和/或数据比较的比较和/或驱动器组件。 一个或多个检查数据存储器被布置在第一总线系统上。 在第二总线系统上,使用第一总线上的存储器的检查数据存储器和存储器保护数据。 本发明还涉及本发明的微处理器系统在汽车控制装置中的应用。