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1. 发明授权

US08578258B2 Method and integrated circuit for increasing the immunity to interference 有权
标题翻译：用于增加抗干扰性的方法和集成电路
公开(公告)号：US08578258B2
公开(公告)日：2013-11-05
申请号：US10590087
申请日：2005-02-17
申请人： Wolfgang Fey , Micha Heinz , Adrian Traskov , Frank Michel
发明人： Wolfgang Fey , Micha Heinz , Adrian Traskov , Frank Michel
IPC分类号： G06F11/00
CPC分类号： G06F11/0772 , G06F11/0724 , G06F11/0736 , G06F11/0739 , G06F11/1645 , G06F11/2215
摘要： Disclosed is a method of improving the immunity to interference of an integrated circuit (16) having error signals transferred between a microprocessor chip or multiple processor μC (1) and an additional component (2). For the transfer, a minimum pulse length that is independent of the clock frequency of the microprocessor or the microprocessors is defined, starting from which a signal on an error line having a defined pulse length is interpreted as an error. Also disclosed is an integrated circuit, which is designed so that the above method is implemented. The circuit has a microprocessor chip or multiple processor microcontroller (1) or microprocessor module and an additional component (2) having separately arranged power elements. The circuit also has pulse extending devices and/or signal delaying devices for the output of error pulses (6, 6′) one after the other through at least one error line (3, 4).
摘要翻译：公开了一种提高在微处理器芯片或多处理器muC（1）与附加部件（2）之间传送的误差信号的集成电路（16）的抗干扰性的方法。对于传输，定义了与微处理器或微处理器的时钟频率无关的最小脉冲长度，从而将具有定义的脉冲长度的误差线上的信号从该脉冲长度解释为误差。还公开了一种集成电路，其被设计为实现上述方法。该电路具有微处理器芯片或多处理器微控制器（1）或微处理器模块以及具有单独布置的功率元件的附加组件（2）。电路还具有脉冲延伸装置和/或信号延迟装置，用于通过至少一个误差线（3,4）一个接一个地输出误差脉冲（6,6'）。

2. 发明授权

US08493703B2 Integrated circuit arrangement for safety critical regulation systems 有权
标题翻译：用于安全关键调节系统的集成电路布置
公开(公告)号：US08493703B2
公开(公告)日：2013-07-23
申请号：US12597369
申请日：2008-04-23
申请人： Andreas Kirschbaum , Mario Engelmann , Frank Michel , Luc van Dijk , Wolfgang Fey , Adrian Traskov , Micha Heinz
发明人： Andreas Kirschbaum , Mario Engelmann , Frank Michel , Luc van Dijk , Wolfgang Fey , Adrian Traskov , Micha Heinz
IPC分类号： H02H5/04
CPC分类号： G06F1/206
摘要： An integrated circuit arrangement on a common chip or chip support, for safety critical applications, in particular for use in control and regulation units for a motor vehicle braking system, including at least one microprocessor system module, which has at least one core processor, provided with at least one ROM and at least one RAM, at least one power module for controlling external users and at least one monitoring module for monitoring at least parts and/or part systems of the circuit arrangement, the circuit arrangement including at least one temperature sensor for recording a chip temperature.
摘要翻译：用于安全关键应用的公共芯片或芯片支架上的集成电路装置，特别是用于机动车辆制动系统的控制和调节单元中，包括至少一个具有至少一个核心处理器的微处理器系统模块具有至少一个ROM和至少一个RAM，用于控制外部用户的至少一个电源模块和用于监视电路装置的至少一部分和/或部分系统的至少一个监视模块，所述电路装置包括至少一个温度传感器用于记录芯片温度。

3. 发明申请

US20100254058A1 INTEGRATED CIRCUIT ARRANGEMENT FOR SAFETY CRITICAL REGULATION SYSTEMS 有权
标题翻译：集成电路安全关键监管系统
公开(公告)号：US20100254058A1
公开(公告)日：2010-10-07
申请号：US12597369
申请日：2008-04-23
申请人： Andreas Kirchbaum , Mario Engelmann , Frank Michel , Luc van Dijk , Wolfgang Fey , Adrian Traskov , Micha Heinz
发明人： Andreas Kirchbaum , Mario Engelmann , Frank Michel , Luc van Dijk , Wolfgang Fey , Adrian Traskov , Micha Heinz
IPC分类号： H02H5/04 , G01K13/00
CPC分类号： G06F1/206
摘要： An integrated circuit arrangement on a common chip or chip support, for safety critical applications, in particular for use in control and regulation units for a motor vehicle braking system, including at least one microprocessor system module, which has at least one core processor, provided with at least one ROM and at least one RAM, at least one power module for controlling external users and at least one monitoring module for monitoring at least parts and/or part systems of the circuit arrangement, the circuit arrangement including at least one temperature sensor for recording a chip temperature.
摘要翻译：用于安全关键应用的公共芯片或芯片支架上的集成电路装置，特别是用于机动车辆制动系统的控制和调节单元中，包括至少一个具有至少一个核心处理器的微处理器系统模块具有至少一个ROM和至少一个RAM，用于控制外部用户的至少一个电源模块和用于监视电路装置的至少一部分和/或部分系统的至少一个监视模块，所述电路装置包括至少一个温度传感器用于记录芯片温度。

4. 发明申请

US20070205930A1 Method and integrated circuit for increasing the immunity to interference 有权
标题翻译：用于增加抗干扰性的方法和集成电路
公开(公告)号：US20070205930A1
公开(公告)日：2007-09-06
申请号：US10590087
申请日：2005-02-17
申请人： Woflgang Fey , Micha Heinz , Adrian Traskov , Frank Michel
发明人： Woflgang Fey , Micha Heinz , Adrian Traskov , Frank Michel
IPC分类号： H03M1/06
CPC分类号： G06F11/0772 , G06F11/0724 , G06F11/0736 , G06F11/0739 , G06F11/1645 , G06F11/2215
摘要： Disclosed is a method of improving the immunity to interference of an integrated circuit (16) having error signals transferred between a microprocessor chip or multiple processor μC (1) and an additional component (2). For the transfer, a minimum pulse length that is independent of the clock frequency of the microprocessor or the microprocessors is defined, starting from which a signal on an error line having a defined pulse length is interpreted as an error. Also disclosed is an integrated circuit, which is designed so that the above method is implemented. The circuit has a microprocessor chip or multiple processor microcontroller (1) or microprocessor module and an additional component (2) having separately arranged power elements. The circuit also has pulse extending devices and/or signal delaying devices for the output of error pulses (6, 6′) one after the other through at least one error line (3, 4).
摘要翻译：公开了一种提高在微处理器芯片或多处理器muC（1）与附加部件（2）之间传送的误差信号的集成电路（16）的抗干扰性的方法。对于传输，定义了与微处理器或微处理器的时钟频率无关的最小脉冲长度，从而将具有定义的脉冲长度的误差线上的信号从该脉冲长度解释为误差。还公开了一种集成电路，其被设计为实现上述方法。该电路具有微处理器芯片或多处理器微控制器（1）或微处理器模块以及具有单独布置的功率元件的附加组件（2）。电路还具有脉冲延伸装置和/或信号延迟装置，用于通过至少一个误差线（3,4）一个接一个地输出误差脉冲（6,6'）。

5. 发明授权

US08347150B2 Method and semiconductor memory with a device for detecting addressing errors 有权
标题翻译：方法和半导体存储器，用于检测寻址错误的装置
公开(公告)号：US08347150B2
公开(公告)日：2013-01-01
申请号：US12517654
申请日：2007-12-05
申请人： Lukusa Didier Kabulepa , Houman Amjadi , Wolfgang Fey , Adrian Traskov
发明人： Lukusa Didier Kabulepa , Houman Amjadi , Wolfgang Fey , Adrian Traskov
IPC分类号： G06F11/26 , G06F11/00
CPC分类号： G11C29/02 , G11C29/024
摘要： A semiconductor memory and a data processing system having hardware for carrying out a method for the improved internal monitoring of addressing circuits in semiconductor memories or in a data processing system, in which logic levels addressing lines are tapped off, the actually selected address or subaddress is represented by additional address bit lines, the actually accessed address/subaddress is recovered using the address bit lines, and the actually selected address/subaddress is compared with the applied address/subaddress, obtained from the additional address bit lines, in order to recognize an error in the addressing circuit.
摘要翻译：半导体存储器和数据处理系统具有用于执行用于改进半导体存储器或数据处理系统中的寻址电路的内部监控的方法的硬件，其中逻辑电平寻址线被分接，实际选择的地址或子地址是由附加地址位线表示，使用地址位线恢复实际访问的地址/子地址，并且将实际选择的地址/子地址与从附加地址位线获得的所施加的地址/子地址进行比较，以便识别寻址电路中的错误。

6. 发明授权

US06901552B1 System for storing data words in a RAM module 失效
标题翻译：用于将数据字存储在RAM模块中的系统
公开(公告)号：US06901552B1
公开(公告)日：2005-05-31
申请号：US10088957
申请日：2000-08-29
申请人： Wolfgang Fey , Adrian Traskov , Jan Truoel
发明人： Wolfgang Fey , Adrian Traskov , Jan Truoel
IPC分类号： G06F11/10 , G06F12/16 , G11C29/42 , H03M13/00
CPC分类号： G06F11/1008 , G06F11/1004 , G06F11/1032 , G06F11/1056
摘要： The present invention describes a method of storing data words in a RAM module which is especially suited for applications that are critical in terms of safety and includes the following steps: producing a check bit word from at least one data word when writing the at least one data word into the RAM module, storing the check bit word, reading out the check bit word when reading out the at least one data word from the RAM module, regenerating the check bit word from the at least one read-out data word, comparing the read-out check bit word with the regenerated check bit word and generating an error message if they do not correspond. This invention further relates to a corresponding circuit configuration.
摘要翻译：本发明描述了一种在RAM模块中存储数据字的方法，该模块特别适用于在安全性方面至关重要的应用，包括以下步骤：当写入至少一个数据字时，从至少一个数据字产生校验位字数据字到RAM模块中，存储检查位字，当从RAM模块读出至少一个数据字时读出校验位字，从至少一个读出的数据字重新产生校验位字，比较读出检查位字与重新生成的校验位字并且如果它们不对应则产生错误消息。本发明还涉及相应的电路配置。

7. 发明授权

US5835041A Circuit for conditioning and digitizing an analog signal 失效
标题翻译：用于调节和数字化模拟信号的电路
公开(公告)号：US5835041A
公开(公告)日：1998-11-10
申请号：US714112
申请日：1997-01-09
申请人： Michael Zydek , Wolfgang Fey , Adrian Traskov
发明人： Michael Zydek , Wolfgang Fey , Adrian Traskov
IPC分类号： B60T8/00 , B60T8/173 , H03M3/02
CPC分类号： B60T8/173 , H03M3/022
摘要： A circuit for conditioning and digitizing an analog input signal that includes a control circuit taking the form of a delta modulator that has a comparator, a clock-controlled flip-flop, a digital accumulator and a digital-to-analog converter. The comparator compares the analog input signal with an adapted signal. The comparator output is conducted to the flip-flop which produces a binary data stream representative of the difference between the comparator inputs. The digital output signal is generated by the accumulator which if fed with an integration constant that is a function of the output signal of the flip-flop. The digital output signal of the accumulator is converted into a square wave signal, which corresponds to the analog input signal, by way of a digital low-pass filter and a threshold value comparator to which the mean value of the digital output signal is supplied as a threshold value.
摘要翻译： PCT No.PCT / EP95 / 00805 Sec。 371日期1997年1月9日 102（e）日期1997年1月9日PCT 1995年3月4日PCT PCT。公开号WO95 / 26079 日期1995年9月28日一种用于调节和数字化模拟输入信号的电路，该电路包括采用具有比较器，时钟控制触发器，数字累加器和数模转换器的增量调制器形式的控制电路转换器。比较器将模拟输入信号与适配信号进行比较。比较器输出被传导到触发器，其产生表示比较器输入之间的差的二进制数据流。数字输出信号由累加器产生，如果馈送有作为触发器的输出信号的函数的积分常数。累加器的数字输出信号通过数字低通滤波器和阈值比较器转换成对应于模拟输入信号的方波信号，数字输出信号的平均值向其提供作为一个阈值。

8. 发明授权

US09529681B2 Microprocessor system for controlling or regulating at least partly safety-critical processes 有权
标题翻译：用于控制或调节至少部分安全关键过程的微处理器系统
公开(公告)号：US09529681B2
公开(公告)日：2016-12-27
申请号：US12063458
申请日：2006-08-02
申请人： Wolfgang Fey , Andreas Kirschbaum , Adrian Traskov
发明人： Wolfgang Fey , Andreas Kirschbaum , Adrian Traskov
IPC分类号： G06F11/00 , G06F11/16 , G06F11/10
CPC分类号： G06F11/1641 , G06F11/1048
摘要： A microprocessor system (50) for controlling or regulating at least partly safety-critical processes, comprising two central processing units (1, 2) integrated in a chip housing, a first and a second bus system, at least one full memory (7) on the first bus system, at least one test data store (51) on the second bus system, which has a reduced store coverage compared to the full memory on the first bus system and in which test data are stored which are connected to data of the memory (7) on the first bus system, and the bus systems comprise comparison and/or driver components which allow the data interchange and/or comparison of data between the two bus systems, and a hardware test data generator (4) is arranged at least on the second bus system, in which case at least part of the full memory on the first bus is additionally backed up using another test data store (5) and test data on the first bus. The invention further relates to the use of the above microprocessor system in motor vehicle controllers.
摘要翻译：一种用于控制或调节至少部分安全关键过程的微处理器系统（50），包括集成在芯片壳体中的两个中央处理单元（1,2），第一和第二总线系统，至少一个完整存储器（7）在第一总线系统上，在第二总线系统上的至少一个测试数据存储器（51），其与第一总线系统上的完整存储器相比具有减小的存储覆盖率，并且其中存储测试数据，其连接到第一总线系统上的存储器（7），以及总线系统包括允许数据交换和/或比较两个总线系统之间的数据的比较和/或驱动器组件，并且硬件测试数据发生器（4）被布置至少在第二总线系统上，在这种情况下，使用另一测试数据存储器（5）和第一总线上的测试数据另外备份第一总线上的至少部分全存储器。本发明还涉及上述微处理器系统在机动车控制器中的应用。

9. 发明授权

US08219860B2 Microprocessor system for controlling at least partly safety-critical processes 有权
标题翻译：用于控制至少部分安全关键过程的微处理器系统
公开(公告)号：US08219860B2
公开(公告)日：2012-07-10
申请号：US12063467
申请日：2006-08-02
申请人： Wolfgang Fey , Andreas Kirschbaum , Adrian Traskov
发明人： Wolfgang Fey , Andreas Kirschbaum , Adrian Traskov
IPC分类号： G01R31/28
CPC分类号： G06F11/1048 , G06F11/1641 , G06F11/1654
摘要： The invention relates to a microprocessor system (60) for controlling and/or regulating at least partly security-critical processes, which system comprises two central processing units (1, 2) integrated into a chip housing, a first and a second bus system, at least one complete memory (7) on the first bus system, and check data in one or more check data memories, said data being related to data of the memory in the first bus system. The check data memory is smaller than the complete memory. The bus systems comprise comparative and/or driver components which facilitate data exchange and/or comparison of data between the two bus systems. The one or more check data memories are arranged on the first bus system. On the second bus system, neither a check data memory nor a memory safeguarding data of the memory on the first bus is used. The invention also relates to the use of the inventive microprocessor system in automotive control devices.
摘要翻译：本发明涉及一种用于控制和/或调节至少部分安全关键性过程的微处理器系统（60），该系统包括集成在芯片壳体中的两个中央处理单元（1,2），第一和第二总线系统，在第一总线系统上的至少一个完整存储器（7），以及检查一个或多个检查数据存储器中的数据，所述数据与第一总线系统中的存储器的数据有关。检查数据存储器小于完整存储器。总线系统包括促进两个总线系统之间的数据交换和/或数据比较的比较和/或驱动器组件。一个或多个检查数据存储器被布置在第一总线系统上。在第二总线系统上，使用第一总线上的存储器的检查数据存储器和存储器保护数据。本发明还涉及本发明的微处理器系统在汽车控制装置中的应用。

10. 发明申请

US20100107006A1 Method and Semiconductor Memory With A Device For Detecting Addressing Errors 有权
标题翻译：用于检测寻址错误的设备的方法和半导体存储器
公开(公告)号：US20100107006A1
公开(公告)日：2010-04-29
申请号：US12517654
申请日：2007-12-05
申请人： Wolfgang Fey , Adrian Traskov , Lukusa Didier Kabulepa , Houman Amjadi
发明人： Wolfgang Fey , Adrian Traskov , Lukusa Didier Kabulepa , Houman Amjadi
IPC分类号： G06F11/07
CPC分类号： G11C29/02 , G11C29/024
摘要： A semiconductor memory and a data processing system having hardware for carrying out a method for the improved internal monitoring of addressing circuits in semiconductor memories or in a data processing system, in which logic levels addressing lines are tapped off, the actually selected address or subaddress is represented by additional address bit lines, the actually accessed address/subaddress is recovered using the address bit lines, and the actually selected address/subaddress is compared with the applied address/subaddress, obtained from the additional address bit lines, in order to recognize an error in the addressing circuit.
摘要翻译：半导体存储器和数据处理系统具有用于执行用于改进半导体存储器或数据处理系统中的寻址电路的内部监控的方法的硬件，其中逻辑电平寻址线被分接，实际选择的地址或子地址是由附加地址位线表示，使用地址位线恢复实际访问的地址/子地址，并且将实际选择的地址/子地址与从附加地址位线获得的所施加的地址/子地址进行比较，以便识别寻址电路中的错误。

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