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1. 发明申请

US20200006272A1 THROUGH-SILICON VIA PILLARS FOR CONNECTING DICE AND METHODS OF ASSEMBLING SAME 审中-公开
公开(公告)号：US20200006272A1
公开(公告)日：2020-01-02
申请号：US16024413
申请日：2018-06-29
申请人： Andreas Augustin , Georg Seidemann , Thomas Wagner , Bernd Waidhas
发明人： Andreas Augustin , Georg Seidemann , Thomas Wagner , Bernd Waidhas
IPC分类号： H01L23/00 , H01L23/538 , H01L23/498 , H01L21/768
摘要： Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.

2. 发明申请

US20190252792A1 ANTENNA WITH GRADED DIELECTIRC AND METHOD OF MAKING THE SAME 审中-公开
公开(公告)号：US20190252792A1
公开(公告)日：2019-08-15
申请号：US15892632
申请日：2018-02-09
申请人： Saravana Maruthamuthu , Bernd Waidhas , Andreas Augustin , Georg Seidemann
发明人： Saravana Maruthamuthu , Bernd Waidhas , Andreas Augustin , Georg Seidemann
IPC分类号： H01Q19/06 , H01Q1/48 , H01Q15/08 , H01L23/66 , H01L23/528 , H01L23/498 , H01L23/522 , H01L23/00 , H01L21/56 , H01L21/3205 , H01L21/48 , H01L21/768 , H01L23/13
CPC分类号： H01Q19/06 , H01L21/32051 , H01L21/4846 , H01L21/56 , H01L21/76802 , H01L21/76877 , H01L23/13 , H01L23/49838 , H01L23/5226 , H01L23/528 , H01L23/66 , H01L24/05 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2223/6616 , H01L2223/6677 , H01L2224/0401 , H01L2224/0557 , H01L2224/16227 , H01L2224/81801 , H01L2924/142 , H01Q1/48 , H01Q15/08
摘要： Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.

3. 发明申请

US20080180160A1 HIGH VOLTAGE DUAL GATE CMOS SWITCHING DEVICE AND METHOD 审中-公开
标题翻译：高电压双门CMOS开关器件及方法
公开(公告)号：US20080180160A1
公开(公告)日：2008-07-31
申请号：US11669594
申请日：2007-01-31
申请人： Andreas Augustin
发明人： Andreas Augustin
IPC分类号： H03K17/687 , H01L27/07 , H01L21/8234
CPC分类号： H01L21/823425 , H01L21/823456 , H01L27/0705 , H01L27/092 , H01L29/0653 , H01L29/7831 , H01L29/7835 , H03K17/687 , H03K2217/0036
摘要： A dual gate drain extension field effect transistor assembly comprises a first FET device having a source, a gate and a drain extension region. The first FET device's gate is electrically coupled to a constant voltage source. A second FET device has a source, a drain, and a gate, and the second FET's drain is electrically to the first FET's source.
摘要翻译：双栅极漏极扩展场效应晶体管组件包括具有源极，栅极和漏极延伸区域的第一FET器件。第一FET器件的栅极电耦合到恒定电压源。第二FET器件具有源极，漏极和栅极，并且第二FET的漏极与第一FET的源极电连接。

4. 发明申请

US20150091167A1 STRESS BUFFER LAYER FOR INTEGRATED MICROELECTROMECHANICAL SYSTEMS (MEMS) 有权
公开(公告)号：US20150091167A1
公开(公告)日：2015-04-02
申请号：US14039157
申请日：2013-09-27
申请人： Christian Geissler , Thorsten Meyer , Gerald Ofner , Reinhard Mahnkopf , Andreas Augustin , Christian Mueller
发明人： Christian Geissler , Thorsten Meyer , Gerald Ofner , Reinhard Mahnkopf , Andreas Augustin , Christian Mueller
IPC分类号： B81C1/00 , B81B7/00
CPC分类号： B81C1/00666 , B81B7/0054 , B81C1/00261 , B81C1/00349 , B81C2203/0136 , B81C2203/0154 , H01L21/568 , H01L23/3135 , H01L24/19 , H01L24/96 , H01L2224/12105 , H01L2224/16145 , H01L2224/24137 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/73207 , H01L2224/73259 , H01L2224/73265 , H01L2224/73277 , H01L2924/1461 , H01L2924/181 , H01L2924/3511 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first and second surfaces, the second surface having an array of external conductive contacts. A microelectromechanical system (MEMS) component is disposed above the first surface of the substrate. A buffer layer is disposed above the MEMS component, the buffer layer having a first Young's modulus. A mold compound is disposed above the buffer layer, the mold compound having a second Young's modulus higher than the first Young's modulus.

5. 发明授权

US09056763B2 Stress buffer layer for integrated microelectromechanical systems (MEMS) 有权
标题翻译：用于集成微机电系统（MEMS）的应力缓冲层
公开(公告)号：US09056763B2
公开(公告)日：2015-06-16
申请号：US14039157
申请日：2013-09-27
申请人： Christian Geissler , Thorsten Meyer , Gerald Ofner , Reinhard Mahnkopf , Andreas Augustin , Christian Mueller
发明人： Christian Geissler , Thorsten Meyer , Gerald Ofner , Reinhard Mahnkopf , Andreas Augustin , Christian Mueller
IPC分类号： H01L23/02 , B81C1/00 , B81B7/00
CPC分类号： B81C1/00666 , B81B7/0054 , B81C1/00261 , B81C1/00349 , B81C2203/0136 , B81C2203/0154 , H01L21/568 , H01L23/3135 , H01L24/19 , H01L24/96 , H01L2224/12105 , H01L2224/16145 , H01L2224/24137 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/73207 , H01L2224/73259 , H01L2224/73265 , H01L2224/73277 , H01L2924/1461 , H01L2924/181 , H01L2924/3511 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first and second surfaces, the second surface having an array of external conductive contacts. A microelectromechanical system (MEMS) component is disposed above the first surface of the substrate. A buffer layer is disposed above the MEMS component, the buffer layer having a first Young's modulus. A mold compound is disposed above the buffer layer, the mold compound having a second Young's modulus higher than the first Young's modulus.
摘要翻译：描述了用于集成微机电系统（MEMS）的应力缓冲层。例如，半导体封装包括具有第一和第二表面的衬底，第二表面具有外部导电触点阵列。微机电系统（MEMS）部件设置在基板的第一表面上方。缓冲层设置在MEMS部件上方，缓冲层具有第一杨氏模量。模具化合物设置在缓冲层上方，模塑料具有高于第一杨氏模量的第二杨氏模量。

6. 发明授权

US06360978B1 Recording and/or reproducing device having a take-up reel and having a tape pull-out assembly which can be positioned radially with respect to the take-up reel 有权
标题翻译：具有卷取卷轴并具有带拉出组件的记录和/或再现装置可以相对于卷带盘径向定位
公开(公告)号：US06360978B1
公开(公告)日：2002-03-26
申请号：US09600192
申请日：2000-07-12
申请人： Andreas Augustin , Franz Kletzl , Robert Nemeth
发明人： Andreas Augustin , Franz Kletzl , Robert Nemeth
IPC分类号： G11B1566
CPC分类号： G11B15/674 , G11B15/67
摘要： A recording and/or reproducing device. A cassette, which contains a magnetic tape and a coupling element connected to the magnetic tape, can be loaded into the device. The device includes a pull-out element which can be coupled to the coupling element so as to form a pull-out assembly. The pull-out assembly can be moved to the reel hub of a take-up reel. A radial positioning structure is provided between the reel hub and the pull-out assembly. The radial positioning structure is formed by two projecting portions, of which a first projecting portion projects from the reel hub and the second projecting portion projects from the pull-out assembly.
摘要翻译：一种记录和/或再现装置。包含磁带和连接到磁带的耦合元件的磁带盒可以装载到装置中。该装置包括可耦合到联接元件以便形成拉出组件的拉出元件。拉出组件可以移动到卷取卷轴的卷轴毂。径向定位结构设置在卷轴轮毂和拉出组件之间。径向定位结构由两个突出部分形成，第一突出部分从卷轴毂突出，第二突出部分从拉出组件突出。

7. 发明授权

US5454644A Foldable object such as information carrier, container and the like 失效
标题翻译：可折叠物体，如信息载体，容器等
公开(公告)号：US5454644A
公开(公告)日：1995-10-03
申请号：US129138
申请日：1993-10-01
申请人： Andreas Augustin
发明人： Andreas Augustin
IPC分类号： B42D1/00 , B42D20060101 , B42D15/00 , B42D15/04 , B65D30/20 , G09B20060101 , G09B29/00 , G09B29/04
CPC分类号： G09B29/04 , B42D15/008
摘要： Foldable object such as information carrier, container or the like, having two wings (1, 2) which can be folded and unfolded about a swing line (3), whereby wing surfaces (4, 5) are provided which fold down between the wings during folding and fold out from between them when the wings are unfolded and the object consists mainly of a shape having projecting and recessed fold lines, so that by folding the wings (1, 2) the wing surfaces (4, 5) can be arranged between the wings and that after unfolding the wings the shape forms an essentially flat surface, the shape having two main fold lines (6, 7) whose intersection point (8) lies on the swing line (3) of the two wings and whereby starting from the each intersection point (25) of the longitudinal fold lines (23, 24) with the main fold lines (6, 7), perpendicularly to the longitudinal fold lines (23, 24), recessed fold lines (26) parallel to the transverse fold line (16) are provided, characterized in that respectively parallel to the longitudinal fold lines (23, 24) and parallel to said recessed fold lines (26), respective projecting fold lines (27, 28) are provided, which intersect each other at a right angle with the intersection point (29) in the main folding lines (6, 7).
摘要翻译： PCT No.PCT / AT92 / 00019 Sec。 371日期：1993年10月10日 102（e）日期1993年10月10日PCT提交1992年2月13日PCT公布。第WO93 / 15916号公报日期：1993年8月19日。可折叠的物体，例如信息载体，容器等，具有可绕着摆动线（3）折叠和展开的两个翼（1,2），由此翼面（4,5）提供了在折叠期间在翅膀之间向下折叠并且当翼展开时从它们之间折叠并且物体主要由具有突出和凹陷的折叠线的形状组成，使得通过将翼（1,2）折叠翼面 4,5）可以布置在翼之间，并且在展开翼之后，形状形成基本平坦的表面，该形状具有两个主要折叠线（6,7），其交点（8）位于摆动线（3）上，并且由此从垂直于纵向折叠线（23,24）的主折叠线（6,7）从纵向折叠线（23,24）的每个交点（25）开始，凹进的折叠提供平行于横向折线（16）的线（26），其特征在于分别平行于纵向折叠线（23,24）并且平行于所述凹陷折叠线（26），设置相应的突出折线（27,28），其与交点（29）成直角相交主折叠线（6,7）。

8. 发明申请

US20140361387A1 CHIP ARRANGEMENT AND METHOD FOR MANUFACTURING A CHIP ARRANGEMENT 有权
标题翻译：芯片布置和制造芯片布置方法
公开(公告)号：US20140361387A1
公开(公告)日：2014-12-11
申请号：US13910133
申请日：2013-06-05
申请人： Thorsten Meyer , Gerald Ofner , Christian Mueller , Reinhard Mahnkopf , Christian Geissler , Andreas Augustin
发明人： Thorsten Meyer , Gerald Ofner , Christian Mueller , Reinhard Mahnkopf , Christian Geissler , Andreas Augustin
IPC分类号： B81B7/00 , B81C1/00
CPC分类号： B81B7/0077 , B81B7/007 , B81B2207/012 , B81B2207/095 , B81C1/00333 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/16146 , H01L2224/16227 , H01L2224/24137 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/73259 , H01L2224/73267 , H01L2924/1431 , H01L2924/1461 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A chip arrangement may include: a mold compound; and a microelectromechanical systems device at least partially embedded in the mold compound.
摘要翻译：芯片布置可以包括：模具化合物; 以及至少部分地嵌入模具化合物中的微机电系统装置。

9. 发明授权

US06624974B2 Recording and/or reproducing apparatus with mechanism for damping vibrations of a component part which cooperates with a record carrier in the form of a tape 有权
标题翻译：记录和/或再现装置，其具有用于阻尼以磁带形式与记录载体协作的部件的振动的机构
公开(公告)号：US06624974B2
公开(公告)日：2003-09-23
申请号：US09793690
申请日：2001-02-26
申请人： Martin Haupt , Harald Bürbaumer , Stefan Bendekovits , Andreas Augustin
发明人： Martin Haupt , Harald Bürbaumer , Stefan Bendekovits , Andreas Augustin
IPC分类号： G11B1560
CPC分类号： G11B15/60 , G11B15/67 , G11B33/08
摘要： In a recording and/or reproducing apparatus (1) having a stationarily mounted and substantially rigid first component part (37) and having at least one pin-like second component part (51, 52) and having a third component part (53) which is movable with respect to the at least one second component part (51, 52), the at least one second component part is fixedly connected to a damping element support (80) and the damping element support (80) extends over the first component part (37) and the damping element support (80) is connected to an elastic damping element (88) which acts upon the first component part (37) under spring load.
摘要翻译：在具有固定安装且基本刚性的第一部件（37）并且具有至少一个销状第二部件（51,52）并且具有第三部件（53）的记录和/或再现装置（1）中，相对于所述至少一个第二部件（51,52）可移动，所述至少一个第二部件固定地连接到阻尼元件支撑件（80），并且所述阻尼元件支撑件（80）在所述第一部件部分（37）和阻尼元件支撑件（80）连接到在弹簧载荷作用在第一部件（37）上的弹性阻尼元件（88）上。

10. 发明申请

US20190272950A1 RESONANT LC TANK PACKAGE AND METHOD OF MANUFACTURE 审中-公开
公开(公告)号：US20190272950A1
公开(公告)日：2019-09-05
申请号：US15910820
申请日：2018-03-02
申请人： Saravana Maruthamuthu , Andreas Augustin , Andreas Wolter
发明人： Saravana Maruthamuthu , Andreas Augustin , Andreas Wolter
IPC分类号： H01F27/40 , H01F27/28 , H01G4/30 , H01G4/005 , H01G4/40 , H01F41/04 , H01L23/522 , H01L23/528
摘要： A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.

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