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1. 发明申请

US20120133406A1 Configurable System for Cancellation of the Mean Value of a Modulated Signal 有权
标题翻译：用于取消调制信号平均值的可配置系统
公开(公告)号：US20120133406A1
公开(公告)日：2012-05-31
申请号：US12956324
申请日：2010-11-30
申请人： Andrea Fant , Luca Sant , Patrick Vernei Torta , Lukas Doerrer
发明人： Andrea Fant , Luca Sant , Patrick Vernei Torta , Lukas Doerrer
IPC分类号： H03K5/01
CPC分类号： H03D1/06 , H03D3/003 , H03D2200/0047 , H03D2200/005 , H03D2200/0052
摘要： Some embodiments of the invention relate to a DC offset correction circuit comprising a feedback loop having a DAC controlled by a reconfigurable ADC, which determines (e.g., tracks) the mean value of a modulated input signal. The circuit operates according to two phase process. In a first “pre-modulation” tracking phase, an input signal is tracked by the ADC, which is configured to output the input signal's mean value as a digital code equivalent to the input mean value. The output of the ADC is provided to a DAC, which provides an analog representation of the mean value to an adder that subtracts the mean value from the modulated input signal to generate a bipolar adjusted input signal. In a second “modulation” phase, the estimated mean value is held constant, so that the bipolar adjusted input signal may be provided to an activated modulation circuit for improved system performance.
摘要翻译：本发明的一些实施例涉及一种DC偏移校正电路，其包括具有由可重构ADC控制的DAC的反馈回路，该可重构ADC确定（例如，跟踪）调制输入信号的平均值。电路根据两相工艺进行工作。在第一个“预调制”跟踪阶段，ADC跟踪输入信号，ADC被配置为将输入信号的平均值输出为与输入平均值相当的数字码。 ADC的输出被提供给DAC，DAC向加法器提供平均值的模拟表示，该加法器从调制输入信号中减去平均值以产生双极调整的输入信号。在第二“调制”阶段，估计的平均值保持不变，从而可以将双极调节的输入信号提供给激活的调制电路，以改善系统性能。

2. 发明授权

US08901996B2 Configurable system for cancellation of the mean value of a modulated signal 有权
标题翻译：用于消除调制信号平均值的可配置系统
公开(公告)号：US08901996B2
公开(公告)日：2014-12-02
申请号：US12956324
申请日：2010-11-30
申请人： Andrea Fant , Luca Sant , Patrick Vernei Torta , Lukas Doerrer
发明人： Andrea Fant , Luca Sant , Patrick Vernei Torta , Lukas Doerrer
IPC分类号： H03D1/06 , H04L25/06 , H03D3/00
CPC分类号： H03D1/06 , H03D3/003 , H03D2200/0047 , H03D2200/005 , H03D2200/0052
摘要： Some embodiments of the invention relate to a DC offset correction circuit comprising a feedback loop having a DAC controlled by a reconfigurable ADC, which determines (e.g., tracks) the mean value of a modulated input signal. The circuit operates according to two phase process. In a first “pre-modulation” tracking phase, an input signal is tracked by the ADC, which is configured to output the input signal's mean value as a digital code equivalent to the input mean value. The output of the ADC is provided to a DAC, which provides an analog representation of the mean value to an adder that subtracts the mean value from the modulated input signal to generate a bipolar adjusted input signal. In a second “modulation” phase, the estimated mean value is held constant, so that the bipolar adjusted input signal may be provided to an activated modulation circuit for improved system performance.
摘要翻译：本发明的一些实施例涉及一种DC偏移校正电路，其包括具有由可重构ADC控制的DAC的反馈回路，该可重构ADC确定（例如，跟踪）调制输入信号的平均值。电路根据两相工艺进行工作。在第一个“预调制”跟踪阶段，ADC跟踪输入信号，ADC被配置为将输入信号的平均值输出为与输入平均值相当的数字码。 ADC的输出被提供给DAC，DAC向加法器提供平均值的模拟表示，该加法器从调制输入信号中减去平均值以产生双极调整的输入信号。在第二“调制”阶段，估计的平均值保持不变，从而可以将双极调节的输入信号提供给激活的调制电路，以改善系统性能。

3. 发明申请

US20120293258A1 INPUT COMMON MODE CIRCUIT FOR A FULLY DIFFERENTIAL AMPLIFIER 有权
标题翻译：输入一个完全差分放大器的通用模式电路
公开(公告)号：US20120293258A1
公开(公告)日：2012-11-22
申请号：US13109737
申请日：2011-05-17
申请人： Andrea Fant , Luca Sant , Patrick Vernei Torta
发明人： Andrea Fant , Luca Sant , Patrick Vernei Torta
IPC分类号： H03F3/45
CPC分类号： H03F3/45085 , H03F3/087 , H03F3/45941 , H03F2203/45134 , H03F2203/45404 , H03F2203/45418 , H03F2203/45424 , H03F2203/45496 , H03F2203/45512 , H03F2203/45702
摘要： This application describes a system for minimizing the common mode voltage drift at the input of a fully differential amplifier. An impedance component is coupled to the inputs and outputs of the differential amplifier. The impedance component optimizes the common mode resistance or impedance to ground without significantly affecting the differential impedance, matches the input common mode voltage to the output common mode voltage and reduces the input common mode voltage drift in presence of leakage currents.
摘要翻译：该应用描述了一种用于最小化全差分放大器输入端的共模电压漂移的系统。阻抗分量耦合到差分放大器的输入和输出。阻抗分量优化了共模电阻或接地阻抗，而不会明显影响差分阻抗，将输入共模电压与输出共模电压相匹配，并在存在漏电流时降低输入共模电压漂移。

4. 发明授权

US08633765B2 Input common mode circuit for a fully differential amplifier 有权
标题翻译：全差分放大器的输入共模电路
公开(公告)号：US08633765B2
公开(公告)日：2014-01-21
申请号：US13109737
申请日：2011-05-17
申请人： Andrea Fant , Luca Sant , Patrick Vernei Torta
发明人： Andrea Fant , Luca Sant , Patrick Vernei Torta
IPC分类号： H03F3/45
CPC分类号： H03F3/45085 , H03F3/087 , H03F3/45941 , H03F2203/45134 , H03F2203/45404 , H03F2203/45418 , H03F2203/45424 , H03F2203/45496 , H03F2203/45512 , H03F2203/45702
摘要： This application describes a system for minimizing the common mode voltage drift at the input of a fully differential amplifier. An impedance component is coupled to the inputs and outputs of the differential amplifier. The impedance component optimizes the common mode resistance or impedance to ground without significantly affecting the differential impedance, matches the input common mode voltage to the output common mode voltage and reduces the input common mode voltage drift in presence of leakage currents.
摘要翻译：该应用描述了一种用于最小化全差分放大器输入端的共模电压漂移的系统。阻抗分量耦合到差分放大器的输入和输出。阻抗分量优化了共模电阻或接地阻抗，而不会明显影响差分阻抗，将输入共模电压与输出共模电压相匹配，并在存在漏电流时降低输入共模电压漂移。

5. 发明授权

US08358164B2 Square wave signal component cancellation 有权
标题翻译：方波信号分量消除
公开(公告)号：US08358164B2
公开(公告)日：2013-01-22
申请号：US12956358
申请日：2010-11-30
申请人： Andrea Fant , Luca Sant , Patrick Vernei Torta
发明人： Andrea Fant , Luca Sant , Patrick Vernei Torta
IPC分类号： H03L5/00
CPC分类号： H04L25/063 , H03C1/06 , H03C2200/0079
摘要： Some embodiments of the invention a circuit configured to apply a time domain processing sequence to a modulated input signal to estimate a mean value of the modulated input signal and to subtract the estimated mean value from the modulated input signal, thereby removing the DC offset from the input signal. In one particular embodiment, the time domain processing sequence is based on integration and differentiation of a demodulated output signal. In such an embodiment, a circuit is configured to integrate a demodulated signal to generate an integrated signal having a triangular shaped output signal. The circuit then measures the slopes of the integrated signal, by differentiation of the triangular shaped integrated signal, and generates an appropriate DC offset correction signal based upon the measured slopes. The DC offset correction signal may be added on top of the actual input signal to cancel the unwanted DC offset component.
摘要翻译：本发明的一些实施例构成为将一个时域处理序列应用于调制输入信号以估计调制输入信号的平均值并从调制输入信号中减去估计平均值的电路，由此从该输入信号。在一个特定实施例中，时域处理序列基于解调输出信号的积分和微分。在这种实施例中，电路被配置为对解调信号进行积分以产生具有三角形输出信号的积分信号。然后，电路通过三角形积分信号的微分来测量积分信号的斜率，并且基于测量的斜率产生适当的DC偏移校正信号。 DC偏移校正信号可以被添加在实际输入信号之上，以消除不想要的DC偏移分量。

6. 发明申请

US20120133412A1 Square Wave Signal Component Cancellation 有权
标题翻译：方波信号分量取消
公开(公告)号：US20120133412A1
公开(公告)日：2012-05-31
申请号：US12956358
申请日：2010-11-30
申请人： Andrea Fant , Luca Sant , Patrick Vernei Torta
发明人： Andrea Fant , Luca Sant , Patrick Vernei Torta
IPC分类号： H03L5/00
CPC分类号： H04L25/063 , H03C1/06 , H03C2200/0079
摘要： Some embodiments of the invention a circuit configured to apply a time domain processing sequence to a modulated input signal to estimate a mean value of the modulated input signal and to subtract the estimated mean value from the modulated input signal, thereby removing the DC offset from the input signal. In one particular embodiment, the time domain processing sequence is based on integration and differentiation of a demodulated output signal. In such an embodiment, a circuit is configured to integrate a demodulated signal to generate an integrated signal having a triangular shaped output signal. The circuit then measures the slopes of the integrated signal, by differentiation of the triangular shaped integrated signal, and generates an appropriate DC offset correction signal based upon the measured slopes. The DC offset correction signal may be added on top of the actual input signal to cancel the unwanted DC offset component.
摘要翻译：本发明的一些实施例构成为将一个时域处理序列应用于调制输入信号以估计调制输入信号的平均值并从调制输入信号中减去估计平均值的电路，由此从该输入信号。在一个特定实施例中，时域处理序列基于解调输出信号的积分和微分。在这种实施例中，电路被配置为对解调信号进行积分以产生具有三角形输出信号的积分信号。然后，电路通过三角形积分信号的微分来测量积分信号的斜率，并且基于测量的斜率产生适当的DC偏移校正信号。 DC偏移校正信号可以被添加在实际输入信号之上，以消除不想要的DC偏移分量。

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