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    • 10. 发明授权
    • Timing budgeting of nested partitions for hierarchical integrated circuit designs
    • 用于分层集成电路设计的嵌套分区的时序预算
    • US08977995B1
    • 2015-03-10
    • US13586495
    • 2012-08-15
    • Sumit AroraOleg LevitskyAmit KumarSushobhit Singh
    • Sumit AroraOleg LevitskyAmit KumarSushobhit Singh
    • G06F17/50
    • G06F17/505G06F2217/84
    • In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a plurality of top level timing constraints and a description of the integrated circuit design defining a hierarchy of partitions having multiple levels with one or more nested partitions; generating timing models for each partition of the plurality of partitions in response to the description of the integrated circuit design; and concurrently generating timing budgets level by level for all partitions at each level, beginning with the lowest level to each next upper level of the hierarchy of the partitions in response to the description of the integrated circuit design, the timing models, and the plurality of top level timing constraints. Please see the detailed description and claims for other embodiments that are respectively disclosed and claimed.
    • 在一个实施例中,公开了一种设计集成电路的方法,包括接收多个顶层定时约束和对使用一个或多个嵌套分区具有多个层次的分区的层次结构的集成电路设计的描述; 响应于所述集成电路设计的描述,为所述多个分区的每个分区生成定时模型; 并且响应于对集成电路设计,定时模型和多个等级的描述,从每个级别的所有分区逐级生成定时预算,从分区的层次结构的最下一级开始到每个下一个较高级别 顶级时间约束。 请参阅分别披露和要求保护的其他实施例的详细描述和权利要求。