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1. 发明申请

US20200065271A1 TECHNOLOGIES FOR FLEXIBLE I/O ENDPOINT ACCELERATION 审中-公开
公开(公告)号：US20200065271A1
公开(公告)日：2020-02-27
申请号：US16366504
申请日：2019-03-27
申请人： Matthew J. Adiletta , Brad Burres , Duane Galbi , Amit Kumar , Yadong Li , Salma Mirza , Jose Niell , Thomas E. Willis , William Duggan
发明人： Matthew J. Adiletta , Brad Burres , Duane Galbi , Amit Kumar , Yadong Li , Salma Mirza , Jose Niell , Thomas E. Willis , William Duggan
IPC分类号： G06F13/20 , G06F13/42
摘要： Technologies for flexible I/O endpoint acceleration include a computing device having a root complex, a soft endpoint coupled to the root complex, and an offload complex coupled to the soft endpoint. The soft endpoint establishes an emulated endpoint hierarchy based on endpoint firmware. The computing device may program the endpoint firmware. The soft endpoint receives an I/O transaction that originates from the root complex and determines whether to process the I/O transaction. The soft endpoint may process the I/O transaction or forward the I/O transaction to the offload complex. The soft endpoint may encapsulate the I/O transaction with metadata and forward the encapsulated transaction to the offload complex. The soft endpoint may store responses from the offload complex in a history buffer and retrieve the responses in response to retried I/O transactions. The I/O transaction may be a PCI Express transaction layer packet. Other embodiments are described and claimed.

2. 发明申请

US20200073846A1 TECHNOLOGIES FOR FLEXIBLE PROTOCOL ACCELERATION 审中-公开
公开(公告)号：US20200073846A1
公开(公告)日：2020-03-05
申请号：US16366496
申请日：2019-03-27
申请人： Matthew J. Adiletta , Bradley Burres , Duane Galbi , Amit Kumar , Yadong Li , Salma Mizra , Jose Niell , Thomas E. Willis , William Duggan
发明人： Matthew J. Adiletta , Bradley Burres , Duane Galbi , Amit Kumar , Yadong Li , Salma Mizra , Jose Niell , Thomas E. Willis , William Duggan
IPC分类号： G06F13/42 , G06F8/60
摘要： Technologies for flexible I/O protocol acceleration include a computing device having a root complex, a smart endpoint coupled to the root complex, and an offload complex coupled to the smart endpoint. The smart endpoint receives an I/O transaction that originates from the root complex and parses the I/O transaction based on an I/O protocol and identifies an I/O command. The smart endpoint may parse the I/O transaction based on endpoint firmware that may be programmed by the computing device. The smart endpoint accelerates the I/O command and provides a smart context to the offload complex. The smart endpoint may copy the I/O command to memory of the smart endpoint or the offload complex. The smart endpoint may identify protocol data based on the I/O command and copy the protocol data to the memory of the smart endpoint or the offload complex. Other embodiments are described and claimed.

3. 发明申请

US20070168768A1 ECC coding for high speed implementation 有权
标题翻译： ECC编码高速实现
公开(公告)号：US20070168768A1
公开(公告)日：2007-07-19
申请号：US11284268
申请日：2005-11-21
申请人： Duane Galbi , Ranjit Loboprabhu , Jose Niell
发明人： Duane Galbi , Ranjit Loboprabhu , Jose Niell
IPC分类号： G06F11/00
CPC分类号： G06F11/1032
摘要： Methods and apparatus for performing error correction code (ECC) coding techniques for high-speed implementations. The ECC code word is structured to facilitate a very fast single-error-detect (SED) that allows state machines to be stopped within a single cycle when an error is detected and enables a corresponding single-error-correct (SEC) operation to be performed over multiple cycles while the state machines are in a suspended mode.
摘要翻译：用于执行用于高速实现的纠错码（ECC）编码技术的方法和装置。 ECC代码字被构造为促进非常快速的单错误检测（SED），其允许在检测到错误时在一个周期内停止状态机，并使相应的单错误校正（SEC）操作成为在状态机处于暂停模式时执行多个周期。

4. 发明公开

US20230325265A1 HARDWARE ACCELERATION IN A NETWORK INTERFACE DEVICE 审中-公开
公开(公告)号：US20230325265A1
公开(公告)日：2023-10-12
申请号：US18334025
申请日：2023-06-13
申请人： Susanne M. Balle , Duane Galbi , Shihwei Roger Chien , Nagabhushan Chitlur , Andrzej Kuriata
发明人： Susanne M. Balle , Duane Galbi , Shihwei Roger Chien , Nagabhushan Chitlur , Andrzej Kuriata
IPC分类号： G06F9/54 , H04L69/18
CPC分类号： G06F9/547 , H04L69/18
摘要： A network interface device connects to one or more endpoint devices and a network. The network interface device receives packet from the network and parses the packet to determine characteristics of the packet, where the packet includes serialized data according to a serialization format. Based on the characteristics, the network interface device determines whether data within the packet can be deserialized using data transformation acceleration hardware provided on the network interface device and which of a plurality of sub-protocols of a multiprotocol interconnect are to be utilized to transport the data to a destination device in the one or more endpoint devices.

5. 发明授权

US5547894A CMOS processing with low and high-current FETs 失效
标题翻译：具有低和高电流FET的CMOS处理
公开(公告)号：US5547894A
公开(公告)日：1996-08-20
申请号：US576184
申请日：1995-12-21
申请人： Jack A. Mandelman , Duane Galbi , James A. Slinkman , William R. Tonti
发明人： Jack A. Mandelman , Duane Galbi , James A. Slinkman , William R. Tonti
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814
摘要： A method of processing CMOS circuits provides up to three types of transistors (standard NFETs, PFETs and high current NFETs) without additional masking steps by the simultaneous implantation of the standard PFET and the high current NFET low doped source and drain implants and a separate implantation of the standard NFET.
摘要翻译：处理CMOS电路的方法提供多达三种类型的晶体管（标准NFET，PFET和高电流NFET），通过同时植入标准PFET和高电流NFET低掺杂源极和漏极注入以及单独注入，不需要额外的掩蔽步骤的标准NFET。

6. 发明申请

US20070006012A1 Engineering the di/dt curve 有权
标题翻译：工程di / dt曲线
公开(公告)号：US20070006012A1
公开(公告)日：2007-01-04
申请号：US11169429
申请日：2005-06-29
申请人： Praveen Mosur , Duane Galbi , Benjamin Cahill
发明人： Praveen Mosur , Duane Galbi , Benjamin Cahill
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： In general, in one aspect, the disclosure describes an apparatus for engineering di/dt. The apparatus includes a plurality of functional blocks to perform different functions. The apparatus also includes a clock source to provide a clock signal to said plurality of functional blocks. At least one gating device is used to regulate application of the clock to the plurality of functional blocks. A controller is included to control the at least one gating device and turning-on of the clock signal.
摘要翻译：通常，在一方面，本公开描述了用于工程di / dt的装置。该装置包括执行不同功能的多个功能块。该装置还包括时钟源，以向所述多个功能块提供时钟信号。至少一个选通装置用于调节时钟对多个功能块的应用。包括一个控制器来控制至少一个选通装置和开启时钟信号。

7. 发明授权

US06366502B1 Circuitry for reading from and writing to memory cells 有权
标题翻译：用于读取和写入存储单元的电路
公开(公告)号：US06366502B1
公开(公告)日：2002-04-02
申请号：US09588168
申请日：2000-06-05
申请人： Steven Charles Docker , Duane Galbi
发明人： Steven Charles Docker , Duane Galbi
IPC分类号： G11C700
CPC分类号： G11C7/1069 , G11C7/1012 , G11C7/1051 , G11C7/1078
摘要： Circuitry for reading from and writing to memory cells of a group of memory cells. The circuitry comprises read circuitry and write circuitry each connectable to bit lines associated with respective ones of the memory cells. The read circuitry is arranged to read from the cells and the write circuitry is arranged to write to the cells. Wherein the read circuitry and write circuitry are configured so that more cells in the group can be simultaneously written to during a write operation than can be simultaneously read from during a read operation.
摘要翻译：用于读取和写入一组存储器单元的存储单元的电路。电路包括读取电路和写入电路，每个读取电路和写入电路可连接到与相应的存储器单元相关联的位线。读取电路被布置为从单元读取并且写入电路被布置成写入单元。其中读取电路和写入电路被配置为使得在写入操作期间可以在读取操作期间同时读取组中的更多单元。

8. 发明授权

US5847575A Method and apparatus for performing switched supply drive in CMOS pad drivers 失效
标题翻译：用于在CMOS焊盘驱动器中执行开关电源驱动的方法和装置
公开(公告)号：US5847575A
公开(公告)日：1998-12-08
申请号：US668170
申请日：1996-06-21
申请人： Duane Galbi , Chris L. Houghton , John A. Kowaleski, Jr.
发明人： Duane Galbi , Chris L. Houghton , John A. Kowaleski, Jr.
IPC分类号： H03K19/003 , H03K19/0185 , H03K17/16
CPC分类号： H03K19/00361
摘要： A driver circuit for limiting electrical noise on a quiescent signal is provided which includes a Transition High Driver circuit, a Transition Low Driver circuit, a Quiescent High Driver circuit, and a Quiescent Low Driver circuit. The driver circuit comprises means for driving an electrical signal with a presumed noisy Transition Power Supply network while it is transitioning from a low voltage level to a high voltage level or vice versa. The signal is driven by the Transition Power Supply network until the electrical signal reaches its quiescent voltage level. At this time, the signal is no longer driven by the Transition Power Supply network but rather by a presumed clean Quiescent Power Supply network. In this manner, noise from transitioning signals is prevented from coupling onto quiescent signals.
摘要翻译：提供了一种用于限制静态信号上的电噪声的驱动电路，其包括转换高驱动器电路，转换低驱动器电路，静态高驱动器电路和静态低驱动器电路。驱动器电路包括用于在从低电压电平转换到高电压电平的同时，推测有噪声的过渡电源网络驱动电信号的装置，反之亦然。信号由转换电源网络驱动，直到电信号达到其静态电压电平。此时，信号不再由过渡电源网络驱动，而是由推定的干净的静态电源网络驱动。以这种方式，防止来自转换信号的噪声被耦合到静态信号。

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