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1. 发明授权

US07355246B2 Memory cell without halo implant 有权
标题翻译：无光晕植入的记忆细胞
公开(公告)号：US07355246B2
公开(公告)日：2008-04-08
申请号：US11268430
申请日：2005-11-07
申请人： Ali Keshavarzi , Stephen H. Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
发明人： Ali Keshavarzi , Stephen H. Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
IPC分类号： H01L29/76
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/0207 , H01L27/0214 , H01L27/105 , H01L27/1052 , H01L27/108
摘要： Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.
摘要翻译：一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷第二种载体。根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结是不偏不倚的一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。

2. 发明授权

US06992339B2 Asymmetric memory cell 有权
公开(公告)号：US06992339B2
公开(公告)日：2006-01-31
申请号：US10750572
申请日：2003-12-31
申请人： Ali Keshavarzi , Stephen H. Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
发明人： Ali Keshavarzi , Stephen H. Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
IPC分类号： H01L27/10
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L29/7841
摘要： Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

3. 发明授权

US06906973B1 Bit-line droop reduction 失效
标题翻译：位线下垂减少
公开(公告)号：US06906973B1
公开(公告)日：2005-06-14
申请号：US10746148
申请日：2003-12-24
申请人： Dinesh Somasekhar , Yibin Ye , Muhammad M. Khellah , Fabrice Paillet , Stephen H. Tang , Ali Keshavarzi , Shih-Lien L. Lu , Vivek K. De
发明人： Dinesh Somasekhar , Yibin Ye , Muhammad M. Khellah , Fabrice Paillet , Stephen H. Tang , Ali Keshavarzi , Shih-Lien L. Lu , Vivek K. De
IPC分类号： G11C7/00 , G11C7/12
CPC分类号： G11C7/12
摘要： Some embodiments provide pre-charge of a bit-line coupled to a memory cell to a reference voltage using a pre-charge device, discharge of the bit-line based on a value stored by the memory cell, injection during the discharge, of a first current into the bit-line using the pre-charge device, and injection, during the discharge, of a second current into a reference bit-line using a second pre-charge device. Also during the discharge, a difference is sensed between a voltage on the bit-line and a voltage on the reference bit-line.
摘要翻译：一些实施例使用预充电器件将耦合到存储器单元的位线预充电至参考电压，基于存储器单元存储的值，放电期间的注入，放电期间的位线放电，使用预充电器件进入位线的第一电流，以及在放电期间使用第二预充电器件将第二电流注入参考位线。此外，在放电期间，在位线上的电压和参考位线上的电压之间感测到差异。

4. 发明授权

US08539303B2 Low overhead error correcting code protection for stored information 有权
标题翻译：存储信息的低开销错误纠正代码保护
公开(公告)号：US08539303B2
公开(公告)日：2013-09-17
申请号：US12973880
申请日：2010-12-20
申请人： Shih-Lien L. Lu , Dinesh Somasekhar
发明人： Shih-Lien L. Lu , Dinesh Somasekhar
IPC分类号： G06F11/00
CPC分类号： H03M13/09 , G06F11/1012 , H03M13/05
摘要： Embodiments of an invention for low overhead error-correcting-code protection for stored information are described are disclosed. In one embodiment, an apparatus includes a data storage structure, a first check value storage structure, a second check value storage structure, and check value generation hardware. The data storage structure is to store a plurality of first data values. The first check value storage structure is to store a plurality of first check values. The second check value storage structure is to store a plurality of second check values. The check value generation hardware is to generate the first check values and the second check values. The first check values provide a first level of error protection for the first data values and the second check values provide a second level of error protection for a plurality of second data values. Each of the plurality of first data value has a first data width, and each of the plurality of second data values has a second data width, the second data width being greater than the first data width. Each of the second data values is a concatenation of one of the first data values and at least another of the first data values.
摘要翻译：公开了用于存储信息的低开销纠错码保护的发明的实施例。在一个实施例中，一种装置包括数据存储结构，第一检查值存储结构，第二检查值存储结构和检查值生成硬件。数据存储结构是存储多个第一数据值。第一检查值存储结构是存储多个第一检查值。第二检查值存储结构是存储多个第二检查值。检查值生成硬件是生成第一检查值和第二检查值。第一检查值为第一数据值提供第一级错误保护，并且第二检查值为多个第二数据值提供第二级别的错误保护。多个第一数据值中的每一个具有第一数据宽度，并且多个第二数据值中的每一个具有第二数据宽度，第二数据宽度大于第一数据宽度。第二数据值中的每一个是第一数据值和第一数据值中的至少另一数据值之一的级联。

5. 发明申请

US20110161783A1 METHOD AND APPARATUS ON DIRECT MATCHING OF CACHE TAGS CODED WITH ERROR CORRECTING CODES (ECC) 审中-公开
标题翻译：使用错误校正码（ECC）编码的缓存标签的直接匹配的方法和设备
公开(公告)号：US20110161783A1
公开(公告)日：2011-06-30
申请号：US12647932
申请日：2009-12-28
申请人： Dinesh Somasekhar , Jeffrey L. Miller , Gunjan H. Pandya , Tsung-Yung Chang , Wei Wu , Shih-Lien L. Lu
发明人： Dinesh Somasekhar , Jeffrey L. Miller , Gunjan H. Pandya , Tsung-Yung Chang , Wei Wu , Shih-Lien L. Lu
IPC分类号： G06F11/10 , G06F12/06
CPC分类号： G06F11/1064 , G06F12/0895
摘要： An apparatus and method is described herein directly matching coded tags. An incoming tag address is encoded with error correction codes (ECCs) to obtain a coded, incoming tag. The coded, incoming tag is directly compared to a stored, coded tag; this comparison result, in one example, yields an m-bit difference between the coded, incoming tag and the stored, coded tag. ECC, in one described embodiment, is able to correct k-bits and detect k+1 bits. As a result, if the m-bit difference is within 2k+2 bits, then valid codes—coded tags—are detected. As an example, if the m-bit difference is less than a hit threshold, such as k-bits, then a hit is determined, while if the m-bit difference is greater than a miss threshold, such as k+1 bits, then a miss is determined.
摘要翻译：这里描述了直接匹配编码标签的装置和方法。输入标签地址用纠错码（ECC）编码，以获得编码的传入标签。编码的输入标签直接与存储的编码标签进行比较; 在一个示例中，该比较结果在编码的输入标签和存储的编码标签之间产生m位差。在一个所描述的实施例中，ECC能够校正k位并检测k + 1位。结果，如果m位差在2k + 2位之内，则检测有效的代码编码标签。例如，如果m位差小于诸如k位的命中阈值，则确定命中，而如果m位差大于诸如k + 1位的未命中阈值，那么一个小姐是决定的。

6. 发明授权

US07514746B2 Floating-body dynamic random access memory and method of fabrication in tri-gate technology 有权
标题翻译：浮动动态随机存取存储器及三栅极技术制造方法
公开(公告)号：US07514746B2
公开(公告)日：2009-04-07
申请号：US11429490
申请日：2006-05-04
申请人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Brian Doyle , Suman Datta , Vivek K. De
发明人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Brian Doyle , Suman Datta , Vivek K. De
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/785 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/66795 , H01L29/7841
摘要： A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.
摘要翻译：浮体动态随机存取存储器件可以包括半导体本体，其具有形成在衬底上的顶表面和横向相对的侧壁。可以在半导体主体的顶表面和半导体本体的横向相对的侧壁上形成栅介质层。栅极电极可以形成在半导体本体的顶表面上的栅极电介质上并与半导体本体的横向相对的侧壁上的栅电介质相邻。栅电极可能仅部分地耗尽半导体本体的区域，并且部分耗尽的区域可以用作逻辑状态的存储节点。

7. 发明授权

US07501316B2 Asymmetric memory cell 有权
标题翻译：不对称记忆单元
公开(公告)号：US07501316B2
公开(公告)日：2009-03-10
申请号：US11268098
申请日：2005-11-07
申请人： Ali Keshavarzi , Stephen H. Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
发明人： Ali Keshavarzi , Stephen H. Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
IPC分类号： H01L21/82
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L29/7841
摘要： Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.
摘要翻译：一些实施例提供了包括体区，源区和漏区的存储单元。主体区域掺杂有第一类型的电荷载流子，源极区域设置在体区中并掺杂有第二类型的电荷载流子，并且漏极区域设置在体区中并掺杂有第二类型的载流子类型。主体区域和源极区域形成第一结，主体区域和漏极区域形成第二结，并且在第一接合点不偏向的情况下，从体区域到源极区域的第一结的导电率基本上在第二接头不偏差的情况下，小于从体区到漏区的第二结的导电性。

8. 发明授权

US07262107B2 Capacitor structure for a logic process 有权
公开(公告)号：US07262107B2
公开(公告)日：2007-08-28
申请号：US11170504
申请日：2005-06-29
申请人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
发明人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
IPC分类号： H01L21/331
CPC分类号： H01L27/108 , H01L27/1085 , H01L28/40
摘要： A manufacturing process modification is disclosed for producing a metal-insulator-metal (MIM) capacitor. The MIM capacitor may be used in memory cells, such as DRAMs, and may also be integrated into logic processing, such as for microprocessors. The processing used to generate the MIM capacitor is adaptable to current logic processing techniques. Other embodiments are described and claimed.

9. 发明授权

US06707755B1 High voltage driver 有权
标题翻译：高压驱动器
公开(公告)号：US06707755B1
公开(公告)日：2004-03-16
申请号：US10316728
申请日：2002-12-11
申请人： Dinesh Somasekhar , Shih-Lien L. Lu
发明人： Dinesh Somasekhar , Shih-Lien L. Lu
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C5/145
摘要： Domino circuits are used to drive cascode circuits in a driver circuit. An output of the driver circuit may be used to provide a high output voltage (higher than the power supply voltage) without overstressing the individual transistors in the driver circuit. In one embodiment, a protection circuit is used to prevent a short circuit between two voltage connections during a transition of the driver circuit output.
摘要翻译： Domino电路用于驱动驱动电路中的共源共享电路。可以使用驱动器电路的输出来提供高输出电压（高于电源电压）而不对驱动器电路中的各个晶体管进行过应力。在一个实施例中，保护电路用于在驱动器电路输出转变期间防止两个电压连接之间的短路。

10. 发明授权

US07391640B2 2-transistor floating-body dram 有权
标题翻译： 2晶体管浮体电容
公开(公告)号：US07391640B2
公开(公告)日：2008-06-24
申请号：US11008666
申请日：2004-12-10
申请人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
发明人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
IPC分类号： G11C11/24 , G11C11/34
CPC分类号： G11C11/405 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.
摘要翻译：动态随机存取存储器包括具有浮体晶体管和位线之间的电路的单元。控制电路的激活以在写入操作期间和在单元未被选择的时间期间在浮体和位线电压之间提供隔离。增加的隔离可以提高性能，例如，通过减少门到体耦合的需要和位线之间的电压摆幅的大小。

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