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1. 发明申请

US20110278570A1 SCALING OF BIPOLAR TRANSISTORS 有权
标题翻译：双极晶体管的放大
公开(公告)号：US20110278570A1
公开(公告)日：2011-11-17
申请号：US13195155
申请日：2011-08-01
申请人： Alvin Jose Joseph , Ramana Murty Malladi , James Albert Slinkman
发明人： Alvin Jose Joseph , Ramana Murty Malladi , James Albert Slinkman
IPC分类号： H01L29/732 , H01L21/331
CPC分类号： H01L29/66272 , G06F17/5009 , G06F17/5036 , G06F17/5068 , G06F2217/12 , H01L21/02532 , H01L21/02595 , H01L21/31111 , H01L21/76224 , H01L21/76229 , H01L21/76232 , H01L21/8249 , H01L27/0207 , H01L29/7322 , Y02P90/265
摘要： Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor.
摘要翻译：双极晶体管结构，双极晶体管的设计和制造方法，设计具有双极晶体管的电路的方法。设计双极晶体管的方法包括：选择双极晶体管的初始设计; 缩放双极晶体管的初始设计以产生双极晶体管的缩放设计; 基于缩放之后双极晶体管的发射极的尺寸来确定双极晶体管的缩放设计的应力补偿是否需要; 并且如果需要对双极型晶体管的缩放设计的应力补偿，则调整缩放设计的沟槽隔离布局级别相对于缩放设计的发射器布局级别的布局的布局，以产生压缩补偿的缩放设计双极晶体管。

2. 发明授权

US08020128B2 Scaling of bipolar transistors 有权
标题翻译：双极晶体管的缩放
公开(公告)号：US08020128B2
公开(公告)日：2011-09-13
申请号：US12493383
申请日：2009-06-29
申请人： Alvin Jose Joseph , Ramana Murty Malladi , James Albert Slinkman
发明人： Alvin Jose Joseph , Ramana Murty Malladi , James Albert Slinkman
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： H01L29/66272 , G06F17/5009 , G06F17/5036 , G06F17/5068 , G06F2217/12 , H01L21/02532 , H01L21/02595 , H01L21/31111 , H01L21/76224 , H01L21/76229 , H01L21/76232 , H01L21/8249 , H01L27/0207 , H01L29/7322 , Y02P90/265
摘要： Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor.
摘要翻译：双极晶体管结构，双极晶体管的设计和制造方法，设计具有双极晶体管的电路的方法。设计双极晶体管的方法包括：选择双极晶体管的初始设计; 缩放双极晶体管的初始设计以产生双极晶体管的缩放设计; 基于缩放之后双极晶体管的发射极的尺寸来确定双极晶体管的缩放设计的应力补偿是否需要; 并且如果需要对双极型晶体管的缩放设计的应力补偿，则调整缩放设计的沟槽隔离布局级别相对于缩放设计的发射器布局级别的布局的布局，以产生压缩补偿的缩放设计双极晶体管。

3. 发明申请

US20100327280A1 SCALING OF BIPOLAR TRANSISTORS 有权
标题翻译：双极晶体管的放大
公开(公告)号：US20100327280A1
公开(公告)日：2010-12-30
申请号：US12493383
申请日：2009-06-29
申请人： Alvin Jose Joseph , Ramana Murty Malladi , James Albert Slinkman
发明人： Alvin Jose Joseph , Ramana Murty Malladi , James Albert Slinkman
IPC分类号： H01L29/73 , G06F17/50 , H01L21/331 , H01L29/04
CPC分类号： H01L29/66272 , G06F17/5009 , G06F17/5036 , G06F17/5068 , G06F2217/12 , H01L21/02532 , H01L21/02595 , H01L21/31111 , H01L21/76224 , H01L21/76229 , H01L21/76232 , H01L21/8249 , H01L27/0207 , H01L29/7322 , Y02P90/265
摘要： Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor.
摘要翻译：双极晶体管结构，双极晶体管的设计和制造方法，设计具有双极晶体管的电路的方法。设计双极晶体管的方法包括：选择双极晶体管的初始设计; 缩放双极晶体管的初始设计以产生双极晶体管的缩放设计; 基于缩放之后双极晶体管的发射极的尺寸来确定双极晶体管的缩放设计的应力补偿是否需要; 并且如果需要对双极晶体管的缩放设计进行应力补偿，则调整缩放设计的沟槽隔离布局级别相对于缩放设计的发射器布局级别的布局的布局，以产生压缩补偿的缩放设计双极晶体管。

4. 发明授权

US08872236B2 Scaling of bipolar transistors 有权
标题翻译：双极晶体管的缩放
公开(公告)号：US08872236B2
公开(公告)日：2014-10-28
申请号：US13195155
申请日：2011-08-01
申请人： Alvin Jose Joseph , Ramana Murty Malladi , James Albert Slinkman
发明人： Alvin Jose Joseph , Ramana Murty Malladi , James Albert Slinkman
IPC分类号： H01L29/66 , G06F17/50 , H01L21/8249 , H01L29/732 , H01L21/762
CPC分类号： H01L29/66272 , G06F17/5009 , G06F17/5036 , G06F17/5068 , G06F2217/12 , H01L21/02532 , H01L21/02595 , H01L21/31111 , H01L21/76224 , H01L21/76229 , H01L21/76232 , H01L21/8249 , H01L27/0207 , H01L29/7322 , Y02P90/265
摘要： Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor.
摘要翻译：双极晶体管结构，双极晶体管的设计和制造方法，设计具有双极晶体管的电路的方法。设计双极晶体管的方法包括：选择双极晶体管的初始设计; 缩放双极晶体管的初始设计以产生双极晶体管的缩放设计; 基于缩放之后双极晶体管的发射极的尺寸来确定双极晶体管的缩放设计的应力补偿是否需要; 并且如果需要对双极型晶体管的缩放设计的应力补偿，则调整缩放设计的沟槽隔离布局级别相对于缩放设计的发射器布局级别的布局的布局，以产生压缩补偿的缩放设计双极晶体管。

5. 发明申请

US20110018060A1 METHOD AND STRUCTURES FOR IMPROVING SUBSTRATE LOSS AND LINEARITY IN SOI SUBSTRATES 有权
标题翻译：改善SOI衬底中衬底损耗和线性的方法和结构
公开(公告)号：US20110018060A1
公开(公告)日：2011-01-27
申请号：US12507150
申请日：2009-07-22
申请人： Alan Bernard Botula , David S. Collins , Alvin Jose Joseph , Howard Smith Landis , James Albert Slinkman , Anthony K. Stamper
发明人： Alan Bernard Botula , David S. Collins , Alvin Jose Joseph , Howard Smith Landis , James Albert Slinkman , Anthony K. Stamper
IPC分类号： H01L27/12 , H01L21/762 , H01L29/06
CPC分类号： H01L21/84 , H01L21/26506 , H01L21/3226 , H01L21/76283 , H01L27/1203
摘要： Methods and structures for improving substrate loss and linearity in SOI substrates. The methods include forming damaged crystal structure regions under the buried oxide layer of SOI substrates and the structures included damaged crystal structure regions under the buried oxide layer of the SOI substrate.
摘要翻译：改善SOI衬底的衬底损耗和线性度的方法和结构。这些方法包括在SOI衬底的掩埋氧化物层下面形成损坏的晶体结构区域，并且其结构包括在SOI衬底的掩埋氧化物层下面的损坏的晶体结构区域。

6. 发明授权

US07772083B2 Trench forming method and structure 失效
标题翻译：沟槽成型方法和结构
公开(公告)号：US07772083B2
公开(公告)日：2010-08-10
申请号：US12344733
申请日：2008-12-29
申请人： Alan Bernard Botula , Michael Lawrence Gautsch , Alvin Jose Joseph , Max Gerald Levy , James Albert Slinkman
发明人： Alan Bernard Botula , Michael Lawrence Gautsch , Alvin Jose Joseph , Max Gerald Levy , James Albert Slinkman
IPC分类号： H01L21/76
CPC分类号： H01L21/76283
摘要： An electrical structure and method of forming. The method includes providing a semiconductor structure comprising a semiconductor substrate, a buried oxide layer (BOX) formed over the semiconductor substrate, and a silicon on insulator layer (SOI) formed over and in contact with the BOX layer. The SOI layer comprises shallow trench isolation (STI) structures formed between electrical devices. A first photoresist layer is formed over the STI structures and the electrical devices. Portions of said first photoresist layer, portions of the STI structures, and portions of the BOX layer are removed resulting in formed trenches. Ion implants are formed within portions of the semiconductor substrate. Remaining portions of the first photoresist layer are removed. A dielectric layer is formed over the electrical devices and within the trenches. A second photoresist layer is formed over the dielectric layer. Portions of the second photoresist layer are removed.
摘要翻译：一种电气结构和成型方法。该方法包括提供半导体结构，其包括半导体衬底，形成在半导体衬底上的掩埋氧化物层（BOX）以及在BOX层上形成并与BOX层接触的绝缘体上硅层。 SOI层包括在电气装置之间形成的浅沟槽隔离（STI）结构。在STI结构和电气装置上形成第一光致抗蚀剂层。所述第一光致抗蚀剂层的部分，STI结构的部分和BOX层的部分被去除，导致形成的沟槽。离子植入物形成在半导体衬底的部分内。去除第一光致抗蚀剂层的剩余部分。电介质层形成在电气装置上并在沟槽内。在电介质层上形成第二光致抗蚀剂层。去除第二光致抗蚀剂层的部分。

7. 发明授权

US08089126B2 Method and structures for improving substrate loss and linearity in SOI substrates 有权
标题翻译：改善SOI衬底的衬底损耗和线性度的方法和结构
公开(公告)号：US08089126B2
公开(公告)日：2012-01-03
申请号：US12507150
申请日：2009-07-22
申请人： Alan Bernard Botula , David S. Collins , Alvin Jose Joseph , Howard Smith Landis , James Albert Slinkman , Anthony K. Stamper
发明人： Alan Bernard Botula , David S. Collins , Alvin Jose Joseph , Howard Smith Landis , James Albert Slinkman , Anthony K. Stamper
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/26506 , H01L21/3226 , H01L21/76283 , H01L27/1203
摘要： Methods and structures for improving substrate loss and linearity in SOI substrates. The methods include forming damaged crystal structure regions under the buried oxide layer of SOI substrates and the structures included damaged crystal structure regions under the buried oxide layer of the SOI substrate.
摘要翻译：改善SOI衬底的衬底损耗和线性度的方法和结构。这些方法包括在SOI衬底的掩埋氧化物层下面形成损坏的晶体结构区域，并且其结构包括在SOI衬底的掩埋氧化物层下面的损坏的晶体结构区域。

8. 发明申请

US20100164075A1 TRENCH FORMING METHOD AND STRUCTURE 失效
标题翻译： TRENCH形成方法和结构
公开(公告)号：US20100164075A1
公开(公告)日：2010-07-01
申请号：US12344733
申请日：2008-12-29
申请人： Alan Bernard Botula , Michael Lawrence Gautsch , Alvin Jose Joseph , Max Gerald Levy , James Albert Slinkman
发明人： Alan Bernard Botula , Michael Lawrence Gautsch , Alvin Jose Joseph , Max Gerald Levy , James Albert Slinkman
IPC分类号： H01L23/58 , H01L21/467
CPC分类号： H01L21/76283
摘要： An electrical structure and method of forming. The method includes providing a semiconductor structure comprising a semiconductor substrate, a buried oxide layer (BOX) formed over the semiconductor substrate, and a silicon on insulator layer (SOI) formed over and in contact with the BOX layer. The SOI layer comprises shallow trench isolation (STI) structures formed between electrical devices. A first photoresist layer is formed over the STI structures and the electrical devices. Portions of said first photoresist layer, portions of the STI structures, and portions of the BOX layer are removed resulting in formed trenches. Ion implants are formed within portions of the semiconductor substrate. Remaining portions of the first photoresist layer are removed. A dielectric layer is formed over the electrical devices and within the trenches. A second photoresist layer is formed over the dielectric layer. Portions of the second photoresist layer are removed.
摘要翻译：一种电气结构和成型方法。该方法包括提供半导体结构，其包括半导体衬底，形成在半导体衬底上的掩埋氧化物层（BOX）以及在BOX层上形成并与BOX层接触的绝缘体上硅层。 SOI层包括在电气装置之间形成的浅沟槽隔离（STI）结构。在STI结构和电气装置上形成第一光致抗蚀剂层。所述第一光致抗蚀剂层的部分，STI结构的部分和BOX层的部分被去除，导致形成的沟槽。离子植入物形成在半导体衬底的部分内。去除第一光致抗蚀剂层的剩余部分。电介质层形成在电气装置上并在沟槽内。在电介质层上形成第二光致抗蚀剂层。去除第二光致抗蚀剂层的部分。

9. 发明授权

US08288821B2 SOI (silicon on insulator) substrate improvements 有权
标题翻译： SOI（绝缘体上硅）衬底改进
公开(公告)号：US08288821B2
公开(公告)日：2012-10-16
申请号：US12547526
申请日：2009-08-26
申请人： Alan Bernard Botula , David S. Collins , Alvin Jose Joseph , Howard Smith Landis , James Albert Slinkman
发明人： Alan Bernard Botula , David S. Collins , Alvin Jose Joseph , Howard Smith Landis , James Albert Slinkman
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L21/84 , H01L27/1203
摘要： A structure, and a method for forming the same. The structure includes a semiconductor substrate which includes a top substrate surface, a buried dielectric layer on the top substrate surface, N active semiconductor regions on the buried dielectric layer, N active devices on the N active semiconductor regions, a plurality of dummy regions on the buried dielectric layer, a protection layer on the N active devices and the N active semiconductor regions, but not on the plurality of dummy regions. The N active devices comprise first active regions which comprise a first material. The plurality of dummy regions comprise first dummy regions which comprise the first material. A first pattern density of the first active regions and the first dummy regions is uniform across the structure. A trench in the buried dielectric layer such that side walls of the trench are aligned with the plurality of dummy regions.
摘要翻译：一种结构及其形成方法。该结构包括半导体衬底，其包括顶部衬底表面，顶部衬底表面上的埋置介质层，埋入介质层上的N个有源半导体区域，N个有源半导体区域上的N个有源器件，埋入介质层，N个有源器件上的保护层和N个有源半导体区域，但不在多个虚拟区域上。 N个有源器件包括构成第一材料的第一有源区。多个虚拟区域包括包含第一材料的第一虚拟区域。第一有源区和第一虚拟区的第一图案密度在整个结构上是均匀的。掩埋介质层中的沟槽，使得沟槽的侧壁与多个虚拟区域对齐。

10. 发明申请

US20100230752A1 SOI (SILICON ON INSULATOR) SUBSTRATE IMPROVEMENTS 有权
标题翻译： SOI（SILICON ON绝缘体）衬底改进
公开(公告)号：US20100230752A1
公开(公告)日：2010-09-16
申请号：US12547526
申请日：2009-08-26
申请人： Alan Bernard Botula , David S. Collins , Alvin Jose Joseph , Howard Smith Landis , James Albert Slinkman
发明人： Alan Bernard Botula , David S. Collins , Alvin Jose Joseph , Howard Smith Landis , James Albert Slinkman
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L21/84 , H01L27/1203
摘要： A structure, and a method for forming the same. The structure includes a semiconductor substrate which includes a top substrate surface, a buried dielectric layer on the top substrate surface, N active semiconductor regions on the buried dielectric layer, N active devices on the N active semiconductor regions, a plurality of dummy regions on the buried dielectric layer, a protection layer on the N active devices and the N active semiconductor regions, but not on the plurality of dummy regions. The N active devices comprise first active regions which comprise a first material. The plurality of dummy regions comprise first dummy regions which comprise the first material. A first pattern density of the first active regions and the first dummy regions is uniform across the structure. A trench in the buried dielectric layer such that side walls of the trench are aligned with the plurality of dummy regions.
摘要翻译：一种结构及其形成方法。该结构包括半导体衬底，其包括顶部衬底表面，顶部衬底表面上的埋置介质层，埋入介质层上的N个有源半导体区域，N个有源半导体区域上的N个有源器件，埋置介质层，N个有源器件上的保护层和N个有源半导体区域，但不在多个虚拟区域上。 N个有源器件包括构成第一材料的第一有源区。多个虚拟区域包括包含第一材料的第一虚拟区域。第一有源区和第一虚拟区的第一图案密度在整个结构上是均匀的。掩埋介质层中的沟槽，使得沟槽的侧壁与多个虚拟区域对齐。

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