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1. 发明授权

US06636995B1 Method of automatic latch insertion for testing application specific integrated circuits 失效
标题翻译：用于测试专用集成电路的自动锁存插入方法
公开(公告)号：US06636995B1
公开(公告)日：2003-10-21
申请号：US09615146
申请日：2000-07-13
申请人： Alvar A. Dean , Joseph A. Iadanza , David E. Lackey , Sebastian T. Ventrone
发明人： Alvar A. Dean , Joseph A. Iadanza , David E. Lackey , Sebastian T. Ventrone
IPC分类号： G01R3128
CPC分类号： G01R31/318357 , G06F17/5022
摘要： A method of testing a digital logic circuit comprises first providing a logic circuit having a plurality of interconnected circuits each having an input and an output; determining a gate level representation of the logic circuit including test nets for determining faults in the circuit; and identifying a portion of the nets which are most difficult to test, including nets which are most difficult to control and nets which are most difficult to observe. The method then includes inserting into the logic circuit control latches for nets which are determined to be most difficult to control and inserting into the logic circuit observation latches for nets which are determined to be most difficult to observe. Using the inserted control latches and observation latches, the method further includes testing the nets which are determined to be most difficult to control and nets which are hardest to observe and determining faults in the circuit. As a result of the method of the present invention, testing is completed in a time faster than if the nets were tested without the control latches and the observation latches. The portion of the nets which are most difficult to test are preferably identified by overall test time impact, and the nets having longest test times are determined to be most difficult to control and most difficult to observe.
摘要翻译：一种测试数字逻辑电路的方法包括：首先提供具有多个互连电路的逻辑电路，每个互连电路具有输入和输出; 确定逻辑电路的门级表示，包括用于确定电路中的故障的测试网; 并且识别最难测试的网的一部分，包括最难控制的网和最难观察的网。该方法然后包括将被确定为最难控制并插入用于被确定为最难观察的网络的逻辑电路观察锁存器的网络的逻辑电路控制锁存器插入。使用插入的控制锁存器和观察锁存器，该方法还包括测试被确定为最难控制的网络，并且网络中难以观察和确定电路中的故障。作为本发明的方法的结果，比没有控制锁存器和观察锁存器测试网络的时间更快地完成测试。最难测试的网的部分优选通过整体测试时间的影响来确定，并且确定具有最长测试时间的网最难以控制并且最难观察。

2. 发明授权

US06792582B1 Concurrent logical and physical construction of voltage islands for mixed supply voltage designs 失效
标题翻译：用于混合电源电压设计的并联电压岛的逻辑和物理构造
公开(公告)号：US06792582B1
公开(公告)日：2004-09-14
申请号：US09713829
申请日：2000-11-15
申请人： John M Cohn , Alvar A. Dean , David J. Hathaway , David E. Lackey , Thomas M. Lepsic , Susan K. Lichtensteiger , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John M Cohn , Alvar A. Dean , David J. Hathaway , David E. Lackey , Thomas M. Lepsic , Susan K. Lichtensteiger , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5068
摘要： Both logical and physical construction of voltage islands is disclosed. A semiconductor chip design is partitioned into “bins”, which are areas of the design. In this way, a semiconductor chip design may be “sliced” into various areas and the areas may then be assigned to various voltage levels. Each bin may be thought of as a voltage island. Circuits in the design can be added to or removed from the various bins, thereby increasing or decreasing the speed and power of the circuits: the speed and power increase if a circuit is placed into a bin assigned a higher voltage, and the speed and power decrease if a circuit is placed into a bin having a lower voltage. The size and location of the bins may also be changed. By iterating these steps, the optimum power consumption may be met while still meeting speed constraints and other criteria. The present invention is applicable to any placement environment, such as an annealing placement tool, that proceeds through successive refinement of the locations of the circuits on the design and in which the placement process may be interrupted to make changes in placement of the logic.
摘要翻译：公开了电压岛的逻辑和物理结构。半导体芯片设计被划分为“箱”，这是设计的区域。以这种方式，可以将半导体芯片设计“切片”成各种区域，然后将这些区域分配给各种电压电平。每个仓可以被认为是电压岛。设计中的电路可以添加到各个机箱中或从各个机箱中移除，从而增加或减少电路的速度和功率：如果将电路放入分配较高电压的箱体中，速度和功率会增加，速度和功率如果将电路放置在具有较低电压的箱中，则减小。还可以改变箱子的大小和位置。通过迭代这些步骤，可以在满足速度限制和其他标准的同时满足最佳功耗。本发明可应用于诸如退火放置工具的任何放置环境，其通过连续细化设计上的电路的位置并且其中可以中断放置过程以使逻辑的放置变化。

3. 发明授权

US06609228B1 Latch clustering for power optimization 失效
标题翻译：锁存聚类功能优化
公开(公告)号：US06609228B1
公开(公告)日：2003-08-19
申请号：US09713571
申请日：2000-11-15
申请人： Paul H. Bergeron , Keith M. Carrig , Alvar A. Dean , Roger P. Gregor , David J. Hathaway , David E. Lackey , Harold E. Reindel , Larry Wissel
发明人： Paul H. Bergeron , Keith M. Carrig , Alvar A. Dean , Roger P. Gregor , David J. Hathaway , David E. Lackey , Harold E. Reindel , Larry Wissel
IPC分类号： G06F1750
CPC分类号： G06F17/5072 , G06F2217/78
摘要： A method and structure of clock optimization including creating an initial placement of clock feeding circuits according to clock signal requirements; identifying clusters of the clock feeding circuits, wherein each cluster includes a distinct clock signal supply device to which each clock feeding circuit within the cluster is connected; changing pin connections between the clock feeding circuits and clock signal supply devices to switch selected ones of the clock feeding circuits to different clusters to reduce lengths of wires between the clock feeding circuits and the clock signal supply devices within each cluster; and adjusting positions of the clock feeding circuits within design constraints to further reduce the lengths of the wires.
摘要翻译：时钟优化的方法和结构，包括根据时钟信号要求创建时钟馈电电路的初始放置; 识别所述时钟馈送电路的簇，其中每个簇包括与所述簇内的每个时钟馈送电路连接的不同的时钟信号供应装置; 改变时钟馈电电路和时钟信号供应装置之间的引脚连接，以将选定的时钟馈电电路切换到不同的簇，以减少时钟馈送电路和每个集群内的时钟信号供应装置之间的导线长度; 以及在设计约束内调整时钟馈电电路的位置，以进一步减少电线的长度。

4. 发明授权

US07996739B2 Avoiding race conditions at clock domain crossings in an edge based scan design 有权
标题翻译：在边缘扫描设计中避免时钟域交叉处的竞争条件
公开(公告)号：US07996739B2
公开(公告)日：2011-08-09
申请号：US12557623
申请日：2009-09-11
申请人： David E. Lackey
发明人： David E. Lackey
IPC分类号： G01R31/28
CPC分类号： G01R31/318594
摘要： A structure, system, and method block clock inputs to clock domains (using a computer). While the clock domain inputs are blocked, the structure, system, and method perform a first timing test only of signals that are transmitted within the clock domains (using the computer) by only observing latches that receive signals from sources within the clock domains. The structure, system, and method also unblock the clock inputs to the clock domains (using the computer). While the clock domain inputs are unblocked, the structure, system, and method perform a second timing test only of signals that are transmitted between the clock domains by only observing latches that receive signals from other clock domains.
摘要翻译：一种结构，系统和方法将时钟域的时钟输入（使用计算机）。当时钟域输入被阻塞时，结构，系统和方法仅通过仅观察从时钟域内的源接收信号的锁存器来执行在时钟域（使用计算机）内发送的信号的第一定时测试。结构，系统和方法还可以解除对时钟域的时钟输入（使用计算机）。当时钟域输入被解除阻塞时，结构，系统和方法仅通过仅观察从其它时钟域接收信号的锁存器来执行在时钟域之间传输的信号的第二定时测试。

5. 发明授权

US07937632B2 Design structure and apparatus for a robust embedded interface 有权
标题翻译：用于强大的嵌入式接口的设计结构和设备
公开(公告)号：US07937632B2
公开(公告)日：2011-05-03
申请号：US12144703
申请日：2008-06-24
申请人： Steven M. Eustis , Kevin W. Gorman , David E. Lackey , Michael R. Ouellette
发明人： Steven M. Eustis , Kevin W. Gorman , David E. Lackey , Michael R. Ouellette
IPC分类号： G11C29/14 , G11C29/50
CPC分类号： G11C29/36 , G11C29/1201 , G11C29/48 , G11C2029/0401
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes an input register coupled to a data processing unit input and a test operation mode and functional operation mode. In the test mode operation, the register operates in a clocked mode such that, during the test operation mode, the register propagates data to the data processing unit in response to a clock signal. In the functional operation mode, the register operates in a data flush mode such that the register propagates data to the data processing unit in response to the data. The functional mode is enabled by a flush enable signal and the test mode is enabled by an opposite state of the flush enable signal.
摘要翻译：设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。该设计结构包括耦合到数据处理单元输入的输入寄存器和测试操作模式和功能操作模式。在测试模式操作中，寄存器以时钟模式操作，使得在测试操作模式期间，寄存器响应于时钟信号将数据传播到数据处理单元。在功能操作模式中，寄存器以数据刷新模式运行，使得寄存器响应于数据将数据传播到数据处理单元。功能模式由刷新使能信号使能，测试模式通过刷新使能信号的相反状态使能。

6. 发明申请

US20090319818A1 METHOD AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE 有权
标题翻译：一种可靠的嵌入式接口的方法和装置
公开(公告)号：US20090319818A1
公开(公告)日：2009-12-24
申请号：US12144686
申请日：2008-06-24
申请人： Steven M. Eustis , Kevin W. Gorman , David E. Lackey , Michael R. Ouellette
发明人： Steven M. Eustis , Kevin W. Gorman , David E. Lackey , Michael R. Ouellette
IPC分类号： G06F1/06
CPC分类号： G01R31/318552 , G11C7/02 , G11C7/04 , G11C7/1072 , G11C29/023 , G11C29/028 , G11C29/1201 , G11C29/12015 , G11C29/48 , G11C2029/5602 , G11C2207/104
摘要： A method is provided for operating an interface between a first unit and a second unit supplying its data. The method includes switching control between LSSD_B and LSSD_C clocks and system clock (CLK) to provide a test mode of operation and a functional mode of operation to optimize setup and hold times depending on conditions under which the unit is operating. In the test mode, data is launched by the LSSD_C clock. In the functional mode, the data is launched by the system clock (CLK) to RAM. A method is also provided to determine which memory inputs should use a circuit that provides adequate setup and hold margins.
摘要翻译：提供一种用于操作第一单元和提供其数据的第二单元之间的接口的方法。该方法包括在LSSD_B和LSSD_C时钟之间的切换控制和系统时钟（CLK），以提供测试操作模式和功能操作模式，以根据单元运行的条件来优化建立和保持时间。在测试模式下，数据由LSSD_C时钟启动。在功能模式下，数据由系统时钟（CLK）发送到RAM。还提供了一种方法来确定哪些存储器输入应该使用提供足够的建立和保持余量的电路。

7. 发明申请

US20090106608A1 APPARATUS AND METHOD FOR SELECTIVELY IMPLEMENTING LAUNCH OFF SCAN CAPABILITY IN AT SPEED TESTING 失效
标题翻译：在速度测试中选择实现启动扫描能力的装置和方法
公开(公告)号：US20090106608A1
公开(公告)日：2009-04-23
申请号：US11874972
申请日：2007-10-19
申请人： Gary D. Grise , Vikram Iyengar , David E. Lackey , Mark R. Taylor
发明人： Gary D. Grise , Vikram Iyengar , David E. Lackey , Mark R. Taylor
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/318541
摘要： An apparatus for selectively implementing launch-off-scan capability in at-speed testing of integrated circuit devices includes a control device configured to selectively disable a master clock signal of a latch structure under test such that a pulse sequence of a system clock signal results in a slave-master-slave clock pulse sequence in the latch structure under test; wherein the control device utilizes the system clock signal as an input thereto and operates in a self-resetting fashion that is timing independent with respect to a scan chain.
摘要翻译：一种用于在集成电路装置的高速测试中选择性地实施发射扫描能力的装置包括控制装置，其被配置为选择性地禁用被测闩锁结构的主时钟信号，使得系统时钟信号的脉冲序列导致被锁存结构中的从主从主时钟脉冲序列; 其中所述控制装置利用所述系统时钟信号作为其输入，并以相对于扫描链定时无关的自复位方式操作。

8. 发明申请

US20080270953A1 IC CHIP AT-FUNCTIONAL-SPEED TESTING WITH PROCESS COVERAGE EVALUATION 有权
标题翻译： IC芯片功能快速测试与过程覆盖评估
公开(公告)号：US20080270953A1
公开(公告)日：2008-10-30
申请号：US11741164
申请日：2007-04-27
申请人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10
摘要： Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust paths representing a non-comprehensive list of AFST robust paths for the IC chip; and re-running the SSTA with the SSTA delay model setup based on the created robust paths. A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip is evaluated based on the process coverage.
摘要翻译：公开了用于评估IC芯片的方法，系统和程序产品。在一个实施例中，该方法包括运行全IC芯片设计的统计静态时序分析（SSTA）; 创建用于IC芯片的功能速度测试（AFST）鲁棒路径，所创建的鲁棒路径表示IC芯片的AFST鲁棒路径的非全面列表; 并基于创建的鲁棒路径，使用SSTA延迟模型设置重新运行SSTA。计算过程覆盖率用于从SSTA运行中进行评估; 并且基于处理覆盖来评估特定的IC芯片。

9. 发明申请

US20080270861A1 NEGATIVE EDGE FLIP-FLOPS FOR MUXSCAN AND EDGE CLOCK COMPATIBLE LSSD 审中-公开
标题翻译：用于MUXSCAN和EDGE时钟兼容LSSD的负边缘FLIPPS
公开(公告)号：US20080270861A1
公开(公告)日：2008-10-30
申请号：US12167470
申请日：2008-07-03
申请人： David E. Lackey
发明人： David E. Lackey
IPC分类号： G01R31/28 , G06F11/25
CPC分类号： G01R31/318541
摘要： A method of synchronous digital operation and scan based testing of an integrated circuit using a flip-flop. The flip-flop including a master latch having an input and a clock pin; a slave latch having an output, a first clock pin and a second clock pin, the slave latch connected to the to the master latch; a first AND gate having a first input, an inverted second input and an output, the output of the first AND gate connected to the first clock pin of the master latch; a second AND gate having a first input, an inverted second input and an output, the output of the second AND gate connected to the second input of the first AND gate and to the first clock pin of the slave latch.
摘要翻译：使用触发器的集成电路的同步数字操作和基于扫描的测试的方法。触发器包括具有输入和时钟引脚的主锁存器; 具有输出的从锁存器，第一时钟引脚和第二时钟引脚，从锁存器连接到主锁存器; 具有第一输入，反相第二输入和输出的第一与门，连接到主锁存器的第一时钟引脚的第一与门的输出; 第二与门，其具有第一输入，反相第二输入和输出，第二与门的输出连接到第一与门的第二输入和从锁存器的第一时钟引脚。

10. 发明授权

US08504971B2 Method and device for selectively adding timing margin in an integrated circuit 有权
标题翻译：用于在集成电路中选择性地添加定时裕度的方法和装置
公开(公告)号：US08504971B2
公开(公告)日：2013-08-06
申请号：US13355099
申请日：2012-01-20
申请人： David E. Lackey , Chandramouili Visweswariah , Paul S. Zuchowski
发明人： David E. Lackey , Chandramouili Visweswariah , Paul S. Zuchowski
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5031 , G01R31/318307 , G01R31/318364
摘要： A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.
摘要翻译：一种方法，系统和集成电路，包括选择性地添加定时裕度。用于集成统计时序和自动测试模式生成（ATPG）以在集成电路中选择性地添加时序裕度的方法包括在芯片设计时识别在制造测试期间“以速度”无法被鲁棒测试的路径，运行统计计时，计算要应用于路径的余量，更新要应用于路径的余量的设计规范，以及基于更新的设计规范优化芯片逻辑。

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