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1. 发明申请

US20060248287A1 Methods and arrangements for reducing latency and snooping cost in non-uniform cache memory architectures 审中-公开
标题翻译：在非均匀缓存存储器架构中减少延迟和窥探成本的方法和安排
公开(公告)号：US20060248287A1
公开(公告)日：2006-11-02
申请号：US11118130
申请日：2005-04-29
申请人： Alper Buyuktosunoglu , Zhigang Hu , Jude Rivers , John Robinson , Xiaowei Shen , Vijayalakshmi Srinivasan
发明人： Alper Buyuktosunoglu , Zhigang Hu , Jude Rivers , John Robinson , Xiaowei Shen , Vijayalakshmi Srinivasan
IPC分类号： G06F13/28
CPC分类号： G06F12/0833 , G06F12/0897 , G06F2212/2542 , G06F2212/271
摘要： Arrangements and methods for providing cache management. Preferably, a buffer arrangement is provided that is adapted to record incoming data into a first cache memory from a second cache memory, convey a data location in the first cache memory upon a prompt for corresponding data, in the event of a hit in the first cache memory, and refer to the second cache memory in the event of a miss in the first cache memory.
摘要翻译：提供缓存管理的安排和方法。优选地，提供缓冲器装置，其适于将来自第二高速缓冲存储器的输入数据记录到第一高速缓冲存储器中，在第一高速缓冲存储器中的第一高速缓冲存储器高速缓冲存储器，并且在第一高速缓冲存储器中未命中的情况下参考第二高速缓冲存储器。

2. 发明申请

US20060155933A1 Cost-conscious pre-emptive cache line displacement and relocation mechanisms 失效
标题翻译：具有成本意识的优先级缓存行位移和迁移机制
公开(公告)号：US20060155933A1
公开(公告)日：2006-07-13
申请号：US11035350
申请日：2005-01-13
申请人： Alper Buyuktosunoglu , Zhigang Hu , Jude Rivers , John Robinson , Xiaowei Shen , Vijayalakshmi Srinivasan
发明人： Alper Buyuktosunoglu , Zhigang Hu , Jude Rivers , John Robinson , Xiaowei Shen , Vijayalakshmi Srinivasan
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/128 , Y02D10/13
摘要： A hardware based method for determining when to migrate cache lines to the cache bank closest to the requesting processor to avoid remote access penalty for future requests. In a preferred embodiment, decay counters are enhanced and used in determining the cost of retaining a line as opposed to replacing it while not losing the data. In one embodiment, a minimization of off-chip communication is sought; this may be particularly useful in a CMP environment.
摘要翻译：一种基于硬件的方法，用于确定何时将高速缓存行迁移到最靠近请求处理器的缓存库，以避免对未来请求的远程访问损失。在优选实施例中，衰减计数器被增强并用于确定保留线的成本，而不是在不丢失数据的情况下替换它。在一个实施例中，寻求片外通信的最小化; 这可能在CMP环境中特别有用。

3. 发明授权

US07454573B2 Cost-conscious pre-emptive cache line displacement and relocation mechanisms 失效
标题翻译：具有成本意识的优先级缓存行位移和迁移机制
公开(公告)号：US07454573B2
公开(公告)日：2008-11-18
申请号：US11035350
申请日：2005-01-13
申请人： Alper Buyuktosunoglu , Zhigang Hu , Jude A. Rivers , John T. Robinson , Xiaowei Shen , Vijayalakshmi Srinivasan
发明人： Alper Buyuktosunoglu , Zhigang Hu , Jude A. Rivers , John T. Robinson , Xiaowei Shen , Vijayalakshmi Srinivasan
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0897 , G06F12/128 , Y02D10/13
摘要： A hardware based method for determining when to migrate cache lines to the cache bank closest to the requesting processor to avoid remote access penalty for future requests. In a preferred embodiment, decay counters are enhanced and used in determining the cost of retaining a line as opposed to replacing it while not losing the data. In one embodiment, a minimization of off-chip communication is sought; this may be particularly useful in a CMP environment.
摘要翻译：一种基于硬件的方法，用于确定何时将高速缓存行迁移到最靠近请求处理器的缓存库，以避免对未来请求的远程访问损失。在优选实施例中，衰减计数器被增强并用于确定保留线的成本，而不是在不丢失数据的情况下替换它。在一个实施例中，寻求片外通信的最小化; 这可能在CMP环境中特别有用。

4. 发明申请

US20090083492A1 COST-CONSCIOUS PRE-EMPTIVE CACHE LINE DISPLACEMENT AND RELOCATION MECHANISMS 审中-公开
标题翻译： COST-CONSCIOUS PRE-CMPE CACHE LINE位移和移动机制
公开(公告)号：US20090083492A1
公开(公告)日：2009-03-26
申请号：US12272612
申请日：2008-11-17
申请人： Alper Buyuktosunoglu , Zhigang Hu , Jude A. Rivers , John T. Robinson , Xiaowei Shen , Vijayalakshmi Srinivasan
发明人： Alper Buyuktosunoglu , Zhigang Hu , Jude A. Rivers , John T. Robinson , Xiaowei Shen , Vijayalakshmi Srinivasan
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0897 , G06F12/128 , Y02D10/13
摘要： A hardware based method for determining when to migrate cache lines to the cache bank closest to the requesting processor to avoid remote access penalty for future requests. In a preferred embodiment, decay counters are enhanced and used in determining the cost of retaining a line as opposed to replacing it while not losing the data. In one embodiment, a minimization of off-chip communication is sought; this may be particularly useful in a CMP environment.
摘要翻译：一种基于硬件的方法，用于确定何时将高速缓存行迁移到最靠近请求处理器的缓存库，以避免对未来请求的远程访问损失。在优选实施例中，衰减计数器被增强并用于确定保留线的成本，而不是在不丢失数据的情况下替换它。在一个实施例中，寻求片外通信的最小化; 这可能在CMP环境中特别有用。

5. 发明申请

US20060112233A1 Enabling and disabling cache bypass using predicted cache line usage 失效
标题翻译：使用预测的缓存线路使用启用和禁用缓存旁路
公开(公告)号：US20060112233A1
公开(公告)日：2006-05-25
申请号：US10993531
申请日：2004-11-19
申请人： Zhigang Hu , John Robinson , Xiaowei Shen , Balaram Sinharoy
发明人： Zhigang Hu , John Robinson , Xiaowei Shen , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0897
摘要： Arrangements and method for enabling and disabling cache bypass in a computer system with a cache hierarchy. Cache bypass status is identified with respect to at least one cache line. A cache line identified as cache bypass enabled is transferred to one or more higher level caches of the cache hierarchy, whereby a next higher level cache in the cache hierarchy is bypassed, while a cache line identified as cache bypass disabled is transferred to one or more higher level caches of the cache hierarchy, whereby a next higher level cache in the cache hierarchy is not bypassed. Included is an arrangement for selectively enabling or disabling cache bypass with respect to at least one cache line based on historical cache access information.
摘要翻译：在具有缓存层次结构的计算机系统中启用和禁用缓存旁路的安排和方法。相对于至少一个高速缓存行来标识缓存旁路状态。标识为启用高速缓存旁路的高速缓存线路被传送到高速缓存层级的一个或多个较高级别的高速缓存，由此旁路高速缓存层级中的下一个较高级别的高速缓存，而被识别为高速缓存旁路禁用的高速缓存线路被转移到一个或多个高速缓存层级的更高级别的高速缓存，从而不绕过高速缓存层级中的下一级高速缓存。包括一种用于基于历史缓存访问信息选择性地启用或禁用相对于至少一个高速缓存行的高速缓存旁路的装置。

6. 发明授权

US07228388B2 Enabling and disabling cache bypass using predicted cache line usage 失效
标题翻译：使用预测的缓存线路使用启用和禁用缓存旁路
公开(公告)号：US07228388B2
公开(公告)日：2007-06-05
申请号：US10993531
申请日：2004-11-19
申请人： Zhigang Hu , John T. Robinson , Xiaowei Shen , Balaram Sinharoy
发明人： Zhigang Hu , John T. Robinson , Xiaowei Shen , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0897
摘要： Arrangements and method for enabling and disabling cache bypass in a computer system with a cache hierarchy. Cache bypass status is identified with respect to at least one cache line. A cache line identified as cache bypass enabled is transferred to one or more higher level caches of the cache hierarchy, whereby a next higher level cache in the cache hierarchy is bypassed, while a cache line identified as cache bypass disabled is transferred to one or more higher level caches of the cache hierarchy, whereby a next higher level cache in the cache hierarchy is not bypassed. Included is an arrangement for selectively enabling or disabling cache bypass with respect to at least one cache line based on historical cache access information.
摘要翻译：在具有缓存层次结构的计算机系统中启用和禁用缓存旁路的安排和方法。相对于至少一个高速缓存行来标识缓存旁路状态。标识为启用高速缓存旁路的高速缓存线路被传送到高速缓存层级的一个或多个较高级别的高速缓存，由此旁路高速缓存层级中的下一个较高级别的高速缓存，而被识别为高速缓存旁路禁用的高速缓存线路被转移到一个或多个高速缓存层级的更高级别的高速缓存，从而不绕过高速缓存层级中的下一级高速缓存。包括一种用于基于历史缓存访问信息选择性地启用或禁用相对于至少一个高速缓存行的高速缓存旁路的装置。

7. 发明授权

US08140764B2 System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memory 有权
标题翻译：用于重新配置具有与下级高速缓冲存储器的扇区相关联的访问位的高速缓冲存储器的系统和与上级高速缓冲存储器的扇区相关联的粒度位
公开(公告)号：US08140764B2
公开(公告)日：2012-03-20
申请号：US12985726
申请日：2011-01-06
申请人： Xiaowei Shen , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
发明人： Xiaowei Shen , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13
摘要： A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.
摘要翻译：提供了一种重新配置高速缓冲存储器的方法。一个方面中的方法可以包括分析访问高速缓冲存储器的执行实体的一个或多个特征，并且基于所分析的一个或多个特征重新配置高速缓存。分析特性的示例可以包括但不限于执行实体使用的数据结构，执行实体的预期参考模式，执行实体的类型，执行实体的热和功耗。等等重新配置可以包括但不限于高速缓冲存储器的相关性，可用于存储数据的高速缓冲存储器的量，高速缓冲存储器的相干粒度，高速缓存存储器的行大小等。

8. 发明授权

US07934061B2 Methods and arrangements to manage on-chip memory to reduce memory latency 有权
标题翻译：管理片上存储器以减少内存延迟的方法和安排
公开(公告)号：US07934061B2
公开(公告)日：2011-04-26
申请号：US12145034
申请日：2008-06-24
申请人： Dilma Menezes da Silva , Elmootazbellah Nabil Elnozahy , Orran Yaakov Krieger , Hazim Shafi , Xiaowei Shen , Balaram Sinharoy , Robert Brett Tremaine
发明人： Dilma Menezes da Silva , Elmootazbellah Nabil Elnozahy , Orran Yaakov Krieger , Hazim Shafi , Xiaowei Shen , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F12/00 , G06F13/00 , G06F3/00
CPC分类号： G06F12/08 , G06F12/0893 , G06F2212/251 , G06F2212/253
摘要： Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.
摘要翻译：考虑通过操作系统提供对软件应用（OCM）的控制的措施来减少处理器所看到的存储器延迟的方法，系统和媒体。许多实施例允许OCM的一部分由软件应用程序通过应用程序接口（API）和由硬件管理的部分来管理。因此，软件应用程序可以提供关于地址范围的指导，以保持靠近处理器，以减少在依赖于缓存控制器策略时通常遇到的不必要的延迟。几个实施例利用处理器内部或处理器节点上的存储器，因此用于该技术的存储器块被称为OCM。

9. 发明授权

US07913041B2 Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hint 有权
标题翻译：基于分析运行时性能数据或软件提示的一个或多个特性的缓存重新配置
公开(公告)号：US07913041B2
公开(公告)日：2011-03-22
申请号：US12130752
申请日：2008-05-30
申请人： Xiaowei Shen , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
发明人： Xiaowei Shen , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13
摘要： A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.
摘要翻译：提供了一种重新配置高速缓冲存储器的方法。一个方面中的方法可以包括分析访问高速缓冲存储器的执行实体的一个或多个特征，并且基于所分析的一个或多个特征重新配置高速缓存。分析特性的示例可以包括但不限于执行实体使用的数据结构，执行实体的预期参考模式，执行实体的类型，执行实体的热和功耗。等等重新配置可以包括但不限于高速缓冲存储器的相关性，可用于存储数据的高速缓冲存储器的量，高速缓冲存储器的相干粒度，高速缓存存储器的行大小等。

10. 发明申请

US20090235035A1 COMPUTER PROGRAM INSTRUCTION ARCHITECTURE, SYSTEM AND PROCESS USING PARTIAL ORDERING FOR ADAPTIVE RESPONSE TO MEMORY LATENCIES 审中-公开
标题翻译：计算机程序指导体系，系统和过程使用部分订购对存储器延迟的自适应响应
公开(公告)号：US20090235035A1
公开(公告)日：2009-09-17
申请号：US12404957
申请日：2009-03-16
申请人： David F. Bacon , Xiaowei Shen
发明人： David F. Bacon , Xiaowei Shen
IPC分类号： G06F12/00
CPC分类号： G06F8/314 , G06F9/30076 , G06F9/30098
摘要： The present invention broadly contemplates braids and fibers, high-level programming constructs which facilitate the creation of programs that are partially ordered, to address the continuing trend of ever-increasing processor speeds and attendant increases in memory latencies. These partial orders can be used to respond adaptively to memory latencies. It is shown how these constructs can be effectively supported with simple and inexpensive instruction set and micro-architectural extensions.
摘要翻译：本发明广泛地考虑了编织物和纤维，高级编程结构，其有助于创建部分排序的程序，以解决不断增长的处理器速度和伴随的存储器延迟增加的持续趋势。这些部分顺序可用于自适应地响应内存延迟。显示了如何通过简单和便宜的指令集和微架构扩展来有效地支持这些构造。

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