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1. 发明授权

US07934061B2 Methods and arrangements to manage on-chip memory to reduce memory latency 有权
标题翻译：管理片上存储器以减少内存延迟的方法和安排
公开(公告)号：US07934061B2
公开(公告)日：2011-04-26
申请号：US12145034
申请日：2008-06-24
申请人： Dilma Menezes da Silva , Elmootazbellah Nabil Elnozahy , Orran Yaakov Krieger , Hazim Shafi , Xiaowei Shen , Balaram Sinharoy , Robert Brett Tremaine
发明人： Dilma Menezes da Silva , Elmootazbellah Nabil Elnozahy , Orran Yaakov Krieger , Hazim Shafi , Xiaowei Shen , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F12/00 , G06F13/00 , G06F3/00
CPC分类号： G06F12/08 , G06F12/0893 , G06F2212/251 , G06F2212/253
摘要： Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.
摘要翻译：考虑通过操作系统提供对软件应用（OCM）的控制的措施来减少处理器所看到的存储器延迟的方法，系统和媒体。许多实施例允许OCM的一部分由软件应用程序通过应用程序接口（API）和由硬件管理的部分来管理。因此，软件应用程序可以提供关于地址范围的指导，以保持靠近处理器，以减少在依赖于缓存控制器策略时通常遇到的不必要的延迟。几个实施例利用处理器内部或处理器节点上的存储器，因此用于该技术的存储器块被称为OCM。

2. 发明申请

US20080263284A1 Methods and Arrangements to Manage On-Chip Memory to Reduce Memory Latency 有权
标题翻译：管理片上存储器以减少内存延迟的方法和布置
公开(公告)号：US20080263284A1
公开(公告)日：2008-10-23
申请号：US12145034
申请日：2008-06-24
申请人： Dilma Menezes da Silva , Elmootazbellah Nabil Elnozahy , Orran Yaakov Krieger , Hazim Shafi , Xiaowei Shen , Balaram Sinharoy , Robert Brett Tremaine
发明人： Dilma Menezes da Silva , Elmootazbellah Nabil Elnozahy , Orran Yaakov Krieger , Hazim Shafi , Xiaowei Shen , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/0893 , G06F2212/251 , G06F2212/253
摘要： Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.
摘要翻译：考虑通过操作系统提供对软件应用（OCM）的控制的措施来减少处理器所看到的存储器延迟的方法，系统和媒体。许多实施例允许OCM的一部分由软件应用程序通过应用程序接口（API）和由硬件管理的部分来管理。因此，软件应用程序可以提供关于地址范围的指导，以保持靠近处理器，以减少在依赖于缓存控制器策略时通常遇到的不必要的延迟。几个实施例利用处理器内部或处理器节点上的存储器，因此用于该技术的存储器块被称为OCM。

3. 发明授权

US07437517B2 Methods and arrangements to manage on-chip memory to reduce memory latency 有权
标题翻译：管理片上存储器以减少内存延迟的方法和安排
公开(公告)号：US07437517B2
公开(公告)日：2008-10-14
申请号：US11032876
申请日：2005-01-11
申请人： Dilma Menezes da Silva , Elmootazbellah Nabil Elnozahy , Orran Yaakov Krieger , Hazim Shafi , Xiaowei Shen , Balaram Sinharoy , Robert Brett Tremaine
发明人： Dilma Menezes da Silva , Elmootazbellah Nabil Elnozahy , Orran Yaakov Krieger , Hazim Shafi , Xiaowei Shen , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F12/00 , G06F13/00 , G06F3/00
CPC分类号： G06F12/08 , G06F12/0893 , G06F2212/251 , G06F2212/253
摘要： Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.
摘要翻译：考虑通过操作系统提供对软件应用（OCM）的控制的措施来减少处理器所看到的存储器延迟的方法，系统和媒体。许多实施例允许OCM的一部分由软件应用程序通过应用程序接口（API）和由硬件管理的部分来管理。因此，软件应用程序可以提供关于地址范围的指导，以保持靠近处理器，以减少在依赖于缓存控制器策略时通常遇到的不必要的延迟。几个实施例利用处理器内部或处理器节点上的存储器，因此用于该技术的存储器块被称为OCM。

4. 发明申请

US20120198459A1 ASSIST THREAD FOR INJECTING CACHE MEMORY IN A MICROPROCESSOR 有权
标题翻译：在微处理器中注入高速缓存存储器的辅助螺纹
公开(公告)号：US20120198459A1
公开(公告)日：2012-08-02
申请号：US13434423
申请日：2012-03-29
申请人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
发明人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F9/46 , G06F12/08
CPC分类号： G06F9/383 , G06F9/3851 , G06F9/4881 , G06F12/0862
摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
摘要翻译：数据处理系统包括具有访问多级缓存存储器的微处理器。微处理器执行从源代码对象编译的主线程。该系统包括用于执行也源自源代码对象的辅助线程的处理器。辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。

5. 发明授权

US08230422B2 Assist thread for injecting cache memory in a microprocessor 有权
标题翻译：协助在微处理器中注入高速缓存的线程
公开(公告)号：US08230422B2
公开(公告)日：2012-07-24
申请号：US11034546
申请日：2005-01-13
申请人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
发明人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F9/46 , G06F9/40 , G06F13/28
CPC分类号： G06F9/383 , G06F9/3851 , G06F9/4881 , G06F12/0862
摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
摘要翻译：数据处理系统包括具有访问多级缓存存储器的微处理器。微处理器执行从源代码对象编译的主线程。该系统包括用于执行也源自源代码对象的辅助线程的处理器。辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。

6. 发明授权

US08949837B2 Assist thread for injecting cache memory in a microprocessor 有权
标题翻译：协助在微处理器中注入高速缓存的线程
公开(公告)号：US08949837B2
公开(公告)日：2015-02-03
申请号：US13434423
申请日：2012-03-29
申请人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
发明人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F9/46 , G06F12/00 , G06F9/38 , G06F12/08 , G06F9/48
CPC分类号： G06F9/383 , G06F9/3851 , G06F9/4881 , G06F12/0862
摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
摘要翻译：数据处理系统包括具有访问多级缓存存储器的微处理器。微处理器执行从源代码对象编译的主线程。该系统包括用于执行也源自源代码对象的辅助线程的处理器。辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。

7. 发明申请

US20060155886A1 Methods and arrangements to manage on-chip memory to reduce memory latency 有权
标题翻译：管理片上存储器以减少内存延迟的方法和安排
公开(公告)号：US20060155886A1
公开(公告)日：2006-07-13
申请号：US11032876
申请日：2005-01-11
申请人： Dilma da Silva , Elmootazbellah Elnozahy , Orran Krieger , Hazim Shafi , Xiaowei Shen , Balaram Sinharoy , Robert Tremaine
发明人： Dilma da Silva , Elmootazbellah Elnozahy , Orran Krieger , Hazim Shafi , Xiaowei Shen , Balaram Sinharoy , Robert Tremaine
IPC分类号： G06F3/00
CPC分类号： G06F12/08 , G06F12/0893 , G06F2212/251 , G06F2212/253
摘要： Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.
摘要翻译：考虑通过操作系统提供对软件应用（OCM）的控制的措施来减少处理器所看到的存储器延迟的方法，系统和媒体。许多实施例允许OCM的一部分由软件应用程序通过应用程序接口（API）和由硬件管理的部分来管理。因此，软件应用程序可以提供关于地址范围的指导，以保持靠近处理器，以减少在依赖于缓存控制器策略时通常遇到的不必要的延迟。几个实施例利用处理器内部或处理器节点上的存储器，因此用于该技术的存储器块被称为OCM。

8. 发明申请

US20060155963A1 Assist thread for injecting cache memory in a microprocessor 有权
公开(公告)号：US20060155963A1
公开(公告)日：2006-07-13
申请号：US11034546
申请日：2005-01-13
申请人： Patrick Bohrer , Orran Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Tremaine
发明人： Patrick Bohrer , Orran Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Tremaine
IPC分类号： G06F9/30
CPC分类号： G06F9/383 , G06F9/3851 , G06F9/4881 , G06F12/0862
摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.

9. 发明申请

US20060064518A1 Method and system for managing cache injection in a multiprocessor system 有权
标题翻译：在多处理器系统中管理缓存注入的方法和系统
公开(公告)号：US20060064518A1
公开(公告)日：2006-03-23
申请号：US10948407
申请日：2004-09-23
申请人： Patrick Bohrer , Ahmed Gheith , Peter Hochschild , Ramakrishnan Rajamony , Hazim Shafi , Balaram Sinharoy
发明人： Patrick Bohrer , Ahmed Gheith , Peter Hochschild , Ramakrishnan Rajamony , Hazim Shafi , Balaram Sinharoy
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and apparatus for managing cache injection in a multiprocessor system reduces processing time associated with direct memory access transfers in a symmetrical multiprocessor (SMP) or a non-uniform memory access (NUMA) multiprocessor environment. The method and apparatus either detect the target processor for DMA completion or direct processing of DMA completion to a particular processor, thereby enabling cache injection to a cache that is coupled with processor that executes the DMA completion routine processing the data injected into the cache. The target processor may be identified by determining the processor handling the interrupt that occurs on completion of the DMA transfer. Alternatively or in conjunction with target processor identification, an interrupt handler may queue a deferred procedure call to the target processor to process the transferred data. In NUMA multiprocessor systems, the completing processor/target memory is chosen for accessibility of the target memory to the processor and associated cache.
摘要翻译：用于管理多处理器系统中的高速缓存注入的方法和装置减少与对称多处理器（SMP）或非均匀存储器访问（NUMA）多处理器环境中的直接存储器访问传输相关联的处理时间。该方法和装置可以检测目标处理器用于DMA完成或直接处理DMA完成到特定处理器，从而使高速缓存注入与执行DMA完成例程的处理器处理注入高速缓存的数据的处理器相连的高速缓存。可以通过确定处理器处理在DMA传输完成时发生的中断来识别目标处理器。或者或与目标处理器识别结合，中断处理程序可以将延迟过程调用排队到目标处理器以处理传送的数据。在NUMA多处理器系统中，选择完成的处理器/目标存储器，以便可访问目标存储器到处理器和相关联的高速缓存。

10. 发明授权

US08255591B2 Method and system for managing cache injection in a multiprocessor system 有权
标题翻译：在多处理器系统中管理缓存注入的方法和系统
公开(公告)号：US08255591B2
公开(公告)日：2012-08-28
申请号：US10948407
申请日：2004-09-23
申请人： Patrick Joseph Bohrer , Ahmed Gheith , Peter Heiner Hochschild , Ramakrishnan Rajamony , Hazim Shafi , Balaram Sinharoy
发明人： Patrick Joseph Bohrer , Ahmed Gheith , Peter Heiner Hochschild , Ramakrishnan Rajamony , Hazim Shafi , Balaram Sinharoy
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and apparatus for managing cache injection in a multiprocessor system reduces processing time associated with direct memory access transfers in a symmetrical multiprocessor (SMP) or a non-uniform memory access (NUMA) multiprocessor environment. The method and apparatus either detect the target processor for DMA completion or direct processing of DMA completion to a particular processor, thereby enabling cache injection to a cache that is coupled with processor that executes the DMA completion routine processing the data injected into the cache. The target processor may be identified by determining the processor handling the interrupt that occurs on completion of the DMA transfer. Alternatively or in conjunction with target processor identification, an interrupt handler may queue a deferred procedure call to the target processor to process the transferred data. In NUMA multiprocessor systems, the completing processor/target memory is chosen for accessibility of the target memory to the processor and associated cache.
摘要翻译：用于管理多处理器系统中的高速缓存注入的方法和装置减少与对称多处理器（SMP）或非均匀存储器访问（NUMA）多处理器环境中的直接存储器访问传输相关联的处理时间。该方法和装置可以检测目标处理器用于DMA完成或直接处理DMA完成到特定处理器，从而使高速缓存注入与执行DMA完成例程的处理器处理注入高速缓存的数据的处理器相连的高速缓存。可以通过确定处理器处理在DMA传输完成时发生的中断来识别目标处理器。或者或与目标处理器识别结合，中断处理程序可以将延迟过程调用排队到目标处理器以处理传送的数据。在NUMA多处理器系统中，选择完成的处理器/目标存储器，以便可访问目标存储器到处理器和相关联的高速缓存。

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