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1. 发明授权

US08787397B2 High speed ring/bus 有权
标题翻译：高速环/公交车
公开(公告)号：US08787397B2
公开(公告)日：2014-07-22
申请号：US12961262
申请日：2010-12-06
申请人： Zvi Regev , Alon Regev
发明人： Zvi Regev , Alon Regev
IPC分类号： H04L12/28 , H04J3/06
CPC分类号： H04L12/422 , H04L12/42
摘要： A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node includes an output port coupled to a media segment that it exclusively controls. And an input port coupled to a media segment that is exclusively controlled by another node of the bus. Each media segment typically includes a plurality of high speed data channels such as electrical transmission lines.
摘要翻译：一种数据通信总线及其操作方法，包括连接到相应的多个媒体段的多个节点。典型的节点包括耦合到其专门控制的媒体段的输出端口。以及耦合到由总线的另一个节点专门控制的媒体段的输入端口。每个媒体段通常包括多个高速数据信道，例如电传输线路。

2. 发明授权

US07302519B2 Distributed content addressable memory 有权
标题翻译：分布式内容可寻址内存
公开(公告)号：US07302519B2
公开(公告)日：2007-11-27
申请号：US11183905
申请日：2005-07-19
申请人： Alon Regev , Zvi Regev
发明人： Alon Regev , Zvi Regev
IPC分类号： G06F12/00
CPC分类号： G06F17/30982
摘要： The present invention provides a large capacity distributed content addressable memory (CAM) made up of a plurality of smaller CAMs interconnected on a high speed data bus. Each of the smaller CAMs is located at a local node on the data bus and configured to receive commands originating from both the local node in which the CAM is located and a local node in which another CAM on the data bus is located. As the resources and the data being stored by all the CAMs are shared through the high speed data bus, the aggregate contents of all the CAMs can be viewed as being stored in a single virtual CAM.
摘要翻译：本发明提供了由在高速数据总线上互连的多个较小的CAM构成的大容量分布式内容可寻址存储器（CAM）。每个较小的CAM位于数据总线上的本地节点上，并被配置为接收源自CAM所在的本地节点的命令和数据总线上另一个CAM所在的本地节点。由于所有CAM所存储的资源和数据都通过高速数据总线共享，所以所有CAM的总体内容可以被看作存储在单个虚拟CAM中。

3. 发明授权

US07280549B2 High speed ring/bus 有权
公开(公告)号：US07280549B2
公开(公告)日：2007-10-09
申请号：US10190554
申请日：2002-07-09
申请人： Zvi Regev , Alon Regev
发明人： Zvi Regev , Alon Regev
IPC分类号： H04L12/28 , H04J3/06
CPC分类号： H04L12/422 , H04L12/42
摘要： A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node includes an output port coupled to a media segment that it exclusively controls. And an input port coupled to a media segment that is exclusively controlled by another node of the bus. Each media segment typically includes a plurality of high speed data channels such as electrical transmission lines.

4. 发明申请

US20070130417A1 CAM with automatic writing to the next free address 有权
标题翻译： CAM自动写入下一个空闲地址
公开(公告)号：US20070130417A1
公开(公告)日：2007-06-07
申请号：US11581747
申请日：2006-10-17
申请人： Alon Regev , Zvi Regev
发明人： Alon Regev , Zvi Regev
IPC分类号： G06F12/00
CPC分类号： G11C15/00
摘要： A method and apparatus for automatically writing non-matching data to a non-valid location within a Content Addressable Memory (CAM) is disclosed. The non-valid locations are determined simultaneously with a search process for a matching address, so that in the event of a non-match, the new data can be written to the invalid locations in a single clock cycle.
摘要翻译：公开了一种用于将非匹配数据自动写入内容寻址存储器（CAM）内的非有效位置的方法和装置。与匹配地址的搜索过程同时确定非有效位置，使得在不匹配的情况下，可以在单个时钟周期内将新数据写入无效位置。

5. 发明授权

US06947301B2 Content addressable memory (CAM) device employing a recirculating shift register for data storage 失效
标题翻译：内容寻址存储器（CAM）装置，采用循环移位寄存器进行数据存储
公开(公告)号：US06947301B2
公开(公告)日：2005-09-20
申请号：US10327075
申请日：2002-12-24
申请人： Alon Regev , Zvi Regev
发明人： Alon Regev , Zvi Regev
IPC分类号： G11C15/00 , G11C19/00 , G11C21/00
CPC分类号： G11C15/00 , G11C19/00 , G11C21/00
摘要： A content addressable memory (CAM) device is described including a plurality of storage locations, each arranged as a recirculating shift register, and plurality of bit comparators each coupled to a predetermined stage of a respective recirculating shift register for comparing the data contents of the predetermined stage with the data contents of a predetermined stage of a comparand register. The CAM is further coupled to a priority encoder for determining the highest priority match address.
摘要翻译：描述内容可寻址存储器（CAM）设备，其包括多个存储位置，每个存储位置被布置为循环移位寄存器，以及多个比特比较器，每个比特比较器耦合到相应的再循环移位寄存器的预定级，用于比较预定具有比较寄存器的预定级的数据内容的阶段。 CAM还被耦合到优先级编码器以确定最高优先级匹配地址。

6. 发明授权

US06934797B2 Counter in CAM word 失效
标题翻译：计数器在CAM字
公开(公告)号：US06934797B2
公开(公告)日：2005-08-23
申请号：US10330206
申请日：2002-12-30
申请人： Alon Regev , Zvi Regev
发明人： Alon Regev , Zvi Regev
IPC分类号： G06F12/00 , G06F17/30
CPC分类号： G06F17/30982
摘要： A method and apparatus for determining the age and frequency of use of words within a Content Addressable Memory (CAM) is disclosed. The CAM utilizes an aging process which determines the level or frequency of activity on every entry in the database, and purges or invalidates entries in the database with very low or infrequent activity.
摘要翻译：公开了一种用于确定内容可寻址存储器（CAM）内的字的使用年龄和频率的方法和装置。 CAM利用老化过程，确定数据库中每个条目的活动级别或频率，并清除或无效数据库中条目非常低或非常频繁的活动。

7. 发明授权

US06934172B2 Priority encoder for successive encoding of multiple matches in a CAM 失效
标题翻译：在CAM中连续编码多个匹配的优先编码器
公开(公告)号：US06934172B2
公开(公告)日：2005-08-23
申请号：US10330269
申请日：2002-12-30
申请人： Alon Regev , Zvi Regev
发明人： Alon Regev , Zvi Regev
IPC分类号： G11C15/00
CPC分类号： G06F7/74 , G11C15/00
摘要： A priority encoder includes a highest priority indicator configured to receive data on multiple content addressable memory (CAM) match lines and flag a highest priority active match line. A multiple match detector detects the presence of multiple simultaneously active match lines. Logic circuitry disables an active match line flagged by the highest priority indicator. The highest priority indicator successively cycles so long as the multiple match detector detects the presence of multiple simultaneously active CAM match lines.
摘要翻译：优先编码器包括配置为在多个可内容寻址存储器（CAM）匹配线上接收数据并标记最高优先级的活动匹配线的最高优先级指示符。多重匹配检测器检测多个同时有效匹配线的存在。逻辑电路禁用由最高优先级指示器标记的活动匹配线。只要多重匹配检测器检测到多个同时活动的CAM匹配线的存在，则最高优先级指示器连续循环。

8. 发明授权

US06781856B2 Tertiary CAM cell 失效
公开(公告)号：US06781856B2
公开(公告)日：2004-08-24
申请号：US10202003
申请日：2002-07-25
申请人： Zvi Regev , Alon Regev
发明人： Zvi Regev , Alon Regev
IPC分类号： G11C1500
CPC分类号： G11C15/043
摘要： A tertiary CAM cell with three bits of storage is disclosed. The three bits of storage are arranged to support three stable states which can be read from the CAM cell without requiring a charge restoration operation. The three stables states are those states where one of the three bits is at a first logical state while the remaining two bits are at a second logical state. The three stables states may be used to encode the three logical states used in a ternary CAM.

9. 发明授权

US07869457B2 High speed ring/bus 有权
标题翻译：高速环/公交车
公开(公告)号：US07869457B2
公开(公告)日：2011-01-11
申请号：US11529632
申请日：2006-09-29
申请人： Zvi Regev , Alon Regev
发明人： Zvi Regev , Alon Regev
IPC分类号： H04L12/42 , H04J3/06
CPC分类号： H04L12/422 , H04L12/42
摘要： A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node includes an output port coupled to a media segment that it exclusively controls. And an input port coupled to a media segment that is exclusively controlled by another node of the bus. Each media segment typically includes a plurality of high speed data channels such as electrical transmission lines.
摘要翻译：一种数据通信总线及其操作方法，包括连接到相应的多个媒体段的多个节点。典型的节点包括耦合到其专门控制的媒体段的输出端口。以及耦合到由总线的另一个节点专门控制的媒体段的输入端口。每个媒体段通常包括多个高速数据信道，例如电传输线路。

10. 发明授权

US07237172B2 Error detection and correction in a CAM 有权
公开(公告)号：US07237172B2
公开(公告)日：2007-06-26
申请号：US10327071
申请日：2002-12-24
申请人： Alon Regev , Zvi Regev
发明人： Alon Regev , Zvi Regev
IPC分类号： H03M13/00 , G11C29/00 , G06F12/00
CPC分类号： G11C15/00 , G06F11/1064 , G11C29/00
摘要： An error detection and correction circuit is connected to at least one memory bank of a CAM device. During background processing (i.e., when the CAM is not performing reading, writing or searching functions) the error detection and correction circuit tests all of the CAM locations that it is connected to in sequence. If an error is detected, the error detection and correction circuit rewrites the CAM location with the correct data. Multiple error correction and detection circuits can be used in the CAM device to test multiple CAM locations simultaneously.

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