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1. 发明申请

US20060004465A1 Fluted intramedullary stem 有权
公开(公告)号：US20060004465A1
公开(公告)日：2006-01-05
申请号：US11139926
申请日：2005-05-27
申请人： Alisha Bergin , David Kelman , Richard Lambert , Todd Swanson
发明人： Alisha Bergin , David Kelman , Richard Lambert , Todd Swanson
IPC分类号： A61F2/36
CPC分类号： A61F2/3662 , A61F2/30771 , A61F2002/30535 , A61F2250/0058
摘要： An intramedullary stem that provides enhanced distal fixation and flexibility and methods for implanting the stem. Certain embodiments of the stem have primary and secondary flutes (or ridges or wedges). Other embodiments have transitional regions.

2. 发明授权

US08229727B2 System and method for incorporating design behavior and external stimulus in microprocessor emulation model feedback using a shared memory 失效
标题翻译：使用共享存储器将设计行为和外部刺激结合在微处理器仿真模型反馈中的系统和方法
公开(公告)号：US08229727B2
公开(公告)日：2012-07-24
申请号：US11621335
申请日：2007-01-09
申请人： Sanjay Gupta , Joseph Anthony Perrie, III , Steven Leonard Roberts , Todd Swanson
发明人： Sanjay Gupta , Joseph Anthony Perrie, III , Steven Leonard Roberts , Todd Swanson
IPC分类号： G06F9/455
CPC分类号： G06F17/5022
摘要： A system and method for incorporating design behavior and external stimulus in microdevice model feedback using a shared memory is presented. The invention describe herein uses the attached memory model to provide additional heuristics to an application executing on an emulation system's device model, which results in a more detail and real-life device emulation. The attached memory model provides a storage area for a runtime software environment to store emulation data, which is subsequently provided to the device model during emulation. The emulation data may include 1) randomization stimuli to the device model, 2) additional runtime data for checking heuristics, and 3) emulation data points that are otherwise not accessible to the device model.
摘要翻译：提出了一种使用共享存储器将设计行为和外部刺激并入微设计模型反馈的系统和方法。本文描述的本发明使用附加的存储器模型来为在仿真系统的设备模型上执行的应用提供附加启发式，这导致更细节和真实的设备仿真。附加的存储器模型为运行时软件环境提供存储区域以存储仿真数据，随后在仿真期间将其提供给设备模型。仿真数据可以包括1）对设备模型的随机化刺激，2）用于检查启发式的附加运行时间数据，以及3）设备模型否则不可访问的仿真数据点。

3. 发明授权

US07720667B2 Method and system for estimating power consumption of integrated circuitry 失效
标题翻译：用于估计集成电路功耗的方法和系统
公开(公告)号：US07720667B2
公开(公告)日：2010-05-18
申请号：US11530100
申请日：2006-09-08
申请人： Rajat Chaudhry , Tilman Gloekler , Daniel L. Stasiak , Todd Swanson
发明人： Rajat Chaudhry , Tilman Gloekler , Daniel L. Stasiak , Todd Swanson
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： First hardware is for executing first software in response to macros that describe integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译：第一硬件是用于响应于描述集成电路的宏执行第一软件，以及响应于第一软件的执行而产生一组常数。第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。

4. 发明申请

US20070041403A1 System and method for communicating instructions and data between a processor and external devices 失效
标题翻译：用于在处理器和外部设备之间传送指令和数据的系统和方法
公开(公告)号：US20070041403A1
公开(公告)日：2007-02-22
申请号：US11207970
申请日：2005-08-19
申请人： Michael Day , Charles Johns , John Liberty , Todd Swanson , Thuong Truong
发明人： Michael Day , Charles Johns , John Liberty , Todd Swanson , Thuong Truong
IPC分类号： G06F15/16 , H04J3/16 , H04J3/22
CPC分类号： H04L49/9078 , H04L49/90 , H04L49/901
摘要： A system and method for communicating instructions and data between a processor and external devices are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译：提供了一种用于在处理器和外部设备之间传送指令和数据的系统和方法。系统和方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。这些通道可以被指定为阻塞或非阻塞。使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。因此，本发明的通道允许处理器保持在低功率状态。

5. 发明授权

US08370780B2 Method and system for estimating power consumption of integrated circuitry 有权
标题翻译：用于估计集成电路功耗的方法和系统
公开(公告)号：US08370780B2
公开(公告)日：2013-02-05
申请号：US12957881
申请日：2010-12-01
申请人： Rajat Chaudhry , Tilman Gloekler , Daniel L. Stasiak , Todd Swanson
发明人： Rajat Chaudhry , Tilman Gloekler , Daniel L. Stasiak , Todd Swanson
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译：设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。设计结构包括用于响应于描述集成电路的宏执行第一软件的第一硬件，以及响应于第一软件的执行而生成一组常数。第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。

6. 发明授权

US07913201B2 Structure for estimating power consumption of integrated circuitry 有权
标题翻译：用于估计集成电路功耗的结构
公开(公告)号：US07913201B2
公开(公告)日：2011-03-22
申请号：US12130644
申请日：2008-05-30
申请人： Rajat Chaudhry , Tilman Gloekler , Daniel L. Stasiak , Todd Swanson
发明人： Rajat Chaudhry , Tilman Gloekler , Daniel L. Stasiak , Todd Swanson
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译：设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。设计结构包括用于响应于描述集成电路的宏执行第一软件的第一硬件，以及响应于第一软件的执行而生成一组常数。第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。

7. 发明申请

US20090217068A1 Structure For Detecting Clock Gating Opportunities In A Pipelined Electronic Circuit Design 有权
标题翻译：用于检测流水线电子电路设计中的时钟门控机制的结构
公开(公告)号：US20090217068A1
公开(公告)日：2009-08-27
申请号：US12347968
申请日：2008-12-31
申请人： Matthew Earl Fernsler, JR. , Hans Mikael Jacobson , Johny Srouji , Todd Swanson
发明人： Matthew Earl Fernsler, JR. , Hans Mikael Jacobson , Johny Srouji , Todd Swanson
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , G06F9/3869 , G06F17/505 , G06F2217/78 , Y02D10/128
摘要： A design structure for a pipeline electronic processor device may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a pipeline electronic circuit that enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit design structure to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.
摘要翻译：用于管道电子处理器设备的设计结构可以体现在用于设计，制造或测试处理器集成电路的机器可读介质中。该设计结构可以体现管道电子电路，该管道电子电路能够通过模拟来识别流水线阶段之间的时钟选通机会，从而在管线的阶段中实现功率节省。在一个实施例中，仿真结果帮助设计者设计流水线电子电路设计结构，以通过在模拟识别的时钟选通机会位置处在管线的阶段之间并入时钟选通电路来实现功率节省。

8. 发明申请

US20090112557A1 System and Method of Automating the Addition of RTL Based Critical Timing Path Counters to Verify Critical Path Coverage of Post-Silicon Software Validation Tools 有权
标题翻译：自动添加基于RTL的关键定时路径计数器的系统和方法，以验证硅片后软件验证工具的关键路径覆盖
公开(公告)号：US20090112557A1
公开(公告)日：2009-04-30
申请号：US11927846
申请日：2007-10-30
申请人： Matthew Edward King , Charles Leverett Meissner , Todd Swanson , Michael Ellett Weissinger
发明人： Matthew Edward King , Charles Leverett Meissner , Todd Swanson , Michael Ellett Weissinger
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system and method for modifying a simulation model and optimizing an application program to produce valid hardware-identified operating conditions that are matched with simulator-identified operating conditions in order to modify a simulator accordingly is presented. A critical path coverage analyzer includes critical path measurement logic into a simulation model that injects errors into the critical path and provides visibility into the number of times that an application program exercises the critical path. The critical path coverage analyzer uses the critical path measurement logic to optimize an application program to adequately exercise and test the critical paths. Once optimized, the critical path coverage analyzer runs the optimized application program on a hardware device to produce hardware-identified operating conditions. The hardware-identified operating conditions are matched against simulator-identified operating conditions. When discrepancies exist, the simulator is modified accordingly to match the hardware-identified operating conditions.
摘要翻译：提出了一种系统和方法，用于修改仿真模型并优化应用程序以产生与模拟器识别的操作条件匹配的有效的硬件识别的操作条件，以便相应地修改模拟器。关键路径覆盖分析器将关键路径测量逻辑包括到将模拟错误注入到关键路径中的模拟模型中，并提供对应用程序执行关键路径的次数的可见性。关键路径覆盖分析仪使用关键路径测量逻辑来优化应用程序，以充分运行和测试关键路径。一旦优化，关键路径覆盖分析仪在硬件设备上运行优化的应用程序，以产生硬件识别的操作条件。硬件识别的操作条件与模拟器识别的操作条件匹配。当存在差异时，相应地修改模拟器以匹配硬件识别的操作条件。

9. 发明申请

US20080288910A1 STRUCTURE FOR ESTIMATING POWER CONSUMPTION OF INTEGRATED CIRCUITRY 有权
标题翻译：用于估计集成电路功耗的结构
公开(公告)号：US20080288910A1
公开(公告)日：2008-11-20
申请号：US12130644
申请日：2008-05-30
申请人： Rajat Chaudhry , Tilman Gloekler , Daniel L. Stasiak , Todd Swanson
发明人： Rajat Chaudhry , Tilman Gloekler , Daniel L. Stasiak , Todd Swanson
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译：设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。设计结构包括用于响应于描述集成电路的宏执行第一软件的第一硬件，以及响应于第一软件的执行而生成一组常数。第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。

10. 发明申请

US20080288230A1 STRUCTURE FOR TESTING AN OPERATION OF INTEGRATED CIRCUITRY 有权
标题翻译：用于测试集成电路运行的结构
公开(公告)号：US20080288230A1
公开(公告)日：2008-11-20
申请号：US12130675
申请日：2008-05-30
申请人： Matthew E. Fernsler , Tilman Gloekler , Sanjay Gupta , Christopher J. Spandikow , Todd Swanson
发明人： Matthew E. Fernsler , Tilman Gloekler , Sanjay Gupta , Christopher J. Spandikow , Todd Swanson
IPC分类号： G06F17/50
CPC分类号： G01R31/31704 , G01R31/318357 , G06F17/5022
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes a general purpose computational resource for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is for: storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.
摘要翻译：设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。该设计结构包括用于执行系统的通用操作的通用计算资源。专用计算资源与通用计算资源相连。专用计算资源用于：存储测试模式，集成电路的描述以及用于测试集成电路的硬件描述; 以及执行用于模拟所述硬件对所述集成电路的测试的响应于所述测试模式的软件。

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