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1. 发明申请

US20080167853A1 Method and System for Testing An Operation of Integrated Circuitry 有权
标题翻译：集成电路运行测试方法与系统
公开(公告)号：US20080167853A1
公开(公告)日：2008-07-10
申请号：US11621361
申请日：2007-01-09
申请人： Matthew E. Fernsler , Tilman Gloekler , Sanjay Gupta , Christopher J. Spandikow , Todd Swanson
发明人： Matthew E. Fernsler , Tilman Gloekler , Sanjay Gupta , Christopher J. Spandikow , Todd Swanson
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/31704 , G01R31/318357 , G06F11/261
摘要： A general purpose computational resource is provided for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is provided for: storing test patterns, a description of integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns
摘要翻译：提供通用计算资源用于执行系统的通用操作。专用计算资源与通用计算资源相连。专用计算资源用于：存储测试模式，集成电路的描述以及用于测试集成电路的硬件描述; 以及执行用于模拟所述硬件对所述集成电路的测试的响应于所述测试模式的软件

2. 发明申请

US20080288230A1 STRUCTURE FOR TESTING AN OPERATION OF INTEGRATED CIRCUITRY 有权
标题翻译：用于测试集成电路运行的结构
公开(公告)号：US20080288230A1
公开(公告)日：2008-11-20
申请号：US12130675
申请日：2008-05-30
申请人： Matthew E. Fernsler , Tilman Gloekler , Sanjay Gupta , Christopher J. Spandikow , Todd Swanson
发明人： Matthew E. Fernsler , Tilman Gloekler , Sanjay Gupta , Christopher J. Spandikow , Todd Swanson
IPC分类号： G06F17/50
CPC分类号： G01R31/31704 , G01R31/318357 , G06F17/5022
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes a general purpose computational resource for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is for: storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.
摘要翻译：设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。该设计结构包括用于执行系统的通用操作的通用计算资源。专用计算资源与通用计算资源相连。专用计算资源用于：存储测试模式，集成电路的描述以及用于测试集成电路的硬件描述; 以及执行用于模拟所述硬件对所述集成电路的测试的响应于所述测试模式的软件。

3. 发明授权

US08027825B2 Structure for testing an operation of integrated circuitry 有权
标题翻译：用于测试集成电路操作的结构
公开(公告)号：US08027825B2
公开(公告)日：2011-09-27
申请号：US12130675
申请日：2008-05-30
申请人： Matthew E. Fernsler , Tilman Gloekler , Sanjay Gupta , Christopher J. Spandikow , Todd Swanson
发明人： Matthew E. Fernsler , Tilman Gloekler , Sanjay Gupta , Christopher J. Spandikow , Todd Swanson
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G01R31/31704 , G01R31/318357 , G06F17/5022
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes a general purpose computational resource for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is for: storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.
摘要翻译：设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。该设计结构包括用于执行系统的通用操作的通用计算资源。专用计算资源与通用计算资源相连。专用计算资源用于：存储测试模式，集成电路的描述以及用于测试集成电路的硬件描述; 以及执行用于模拟所述硬件对所述集成电路的测试的响应于所述测试模式的软件。

4. 发明授权

US08006155B2 Testing an operation of integrated circuitry 有权
标题翻译：测试集成电路的操作
公开(公告)号：US08006155B2
公开(公告)日：2011-08-23
申请号：US11621361
申请日：2007-01-09
申请人： Matthew E. Fernsler , Tilman Gloekler , Sanjay Gupta , Christopher J. Spandikow , Todd Swanson
发明人： Matthew E. Fernsler , Tilman Gloekler , Sanjay Gupta , Christopher J. Spandikow , Todd Swanson
IPC分类号： G01R31/28
CPC分类号： G06F17/5022 , G01R31/31704 , G01R31/318357 , G06F11/261
摘要： A general purpose computational resource is provided for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is provided for: storing test patterns, a description of integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.
摘要翻译：提供通用计算资源用于执行系统的通用操作。专用计算资源与通用计算资源相连。专用计算资源用于：存储测试模式，集成电路的描述以及用于测试集成电路的硬件描述; 以及执行用于模拟所述硬件对所述集成电路的测试的响应于所述测试模式的软件。

5. 发明授权

US07472034B2 System and method for test generation for system level verification using parallel algorithms 失效
标题翻译：使用并行算法进行系统级验证的测试生成系统和方法
公开(公告)号：US07472034B2
公开(公告)日：2008-12-30
申请号：US11758357
申请日：2007-06-05
申请人： Sanjay Gupta , Steven L. Roberts , Christopher J. Spandikow
发明人： Sanjay Gupta , Steven L. Roberts , Christopher J. Spandikow
IPC分类号： G01M19/00 , G06F19/00 , G01R31/00
CPC分类号： G06F11/263
摘要： A system and method for test generation for system level verification using parallel algorithms are provided. The present invention generates test patterns for system level tests by exploiting the scalability of parallel algorithms while allowing for data set coloring and expected result checking. Based on the characteristics of the system being tested an iterative parallel algorithm is selected from a plurality of possible parallel algorithms. The selected parallel algorithm is then separated into separate program statements for execution by a plurality of processors. A serial version of the selected algorithm is executed to generate a set of expected results. The devised parallel version of the selected algorithm is then run to generate a set of test result data which is compared to the set of expected results. If the two sets of data match, it is determined that the system is operating correctly.
摘要翻译：提供了一种使用并行算法进行系统级验证的测试生成系统和方法。本发明通过利用并行算法的可扩展性同时允许数据集着色和预期结果检查来生成用于系统级测试的测试模式。基于被测系统的特征，从多个可能的并行算法中选择迭代并行算法。然后将所选择的并行算法分离成单独的程序语句以供多个处理器执行。执行所选算法的串行版本以产生一组预期结果。然后运行所选算法的设计的并行版本以生成与一组预期结果进行比较的一组测试结果数据。如果两组数据匹配，则确定系统正常运行。

6. 发明授权

US07260495B2 System and method for test generation for system level verification using parallel algorithms 有权
标题翻译：使用并行算法进行系统级验证的测试生成系统和方法
公开(公告)号：US07260495B2
公开(公告)日：2007-08-21
申请号：US11146987
申请日：2005-06-06
申请人： Sanjay Gupta , Steven L. Roberts , Christopher J. Spandikow
发明人： Sanjay Gupta , Steven L. Roberts , Christopher J. Spandikow
IPC分类号： G06F11/00
CPC分类号： G06F11/263
摘要： A system and method for test generation for system level verification using parallel algorithms are provided. The present invention generates test patterns for system level tests by exploiting the scalability of parallel algorithms while allowing for data set coloring and expected result checking. Based on the characteristics of the system being tested an iterative parallel algorithm is selected from a plurality of possible parallel algorithms. The selected parallel algorithm is then separated into separate program statements for execution by a plurality of processors. A serial version of the selected algorithm is executed to generate a set of expected results. The devised parallel version of the selected algorithm is then run to generate a set of test result data which is compared to the set of expected results. If the two sets of data match, it is determined that the system is operating correctly.
摘要翻译：提供了一种使用并行算法进行系统级验证的测试生成系统和方法。本发明通过利用并行算法的可扩展性同时允许数据集着色和预期结果检查来生成用于系统级测试的测试模式。基于被测系统的特征，从多个可能的并行算法中选择迭代并行算法。然后将所选择的并行算法分离成单独的程序语句以供多个处理器执行。执行所选算法的串行版本以产生一组预期结果。然后运行所选算法的设计的并行版本以生成与一组预期结果进行比较的一组测试结果数据。如果两组数据匹配，则确定系统正常运行。

7. 发明授权

US08229727B2 System and method for incorporating design behavior and external stimulus in microprocessor emulation model feedback using a shared memory 失效
标题翻译：使用共享存储器将设计行为和外部刺激结合在微处理器仿真模型反馈中的系统和方法
公开(公告)号：US08229727B2
公开(公告)日：2012-07-24
申请号：US11621335
申请日：2007-01-09
申请人： Sanjay Gupta , Joseph Anthony Perrie, III , Steven Leonard Roberts , Todd Swanson
发明人： Sanjay Gupta , Joseph Anthony Perrie, III , Steven Leonard Roberts , Todd Swanson
IPC分类号： G06F9/455
CPC分类号： G06F17/5022
摘要： A system and method for incorporating design behavior and external stimulus in microdevice model feedback using a shared memory is presented. The invention describe herein uses the attached memory model to provide additional heuristics to an application executing on an emulation system's device model, which results in a more detail and real-life device emulation. The attached memory model provides a storage area for a runtime software environment to store emulation data, which is subsequently provided to the device model during emulation. The emulation data may include 1) randomization stimuli to the device model, 2) additional runtime data for checking heuristics, and 3) emulation data points that are otherwise not accessible to the device model.
摘要翻译：提出了一种使用共享存储器将设计行为和外部刺激并入微设计模型反馈的系统和方法。本文描述的本发明使用附加的存储器模型来为在仿真系统的设备模型上执行的应用提供附加启发式，这导致更细节和真实的设备仿真。附加的存储器模型为运行时软件环境提供存储区域以存储仿真数据，随后在仿真期间将其提供给设备模型。仿真数据可以包括1）对设备模型的随机化刺激，2）用于检查启发式的附加运行时间数据，以及3）设备模型否则不可访问的仿真数据点。

8. 发明申请

US20080167854A1 System and Method for Incorporating Design Behavior and External Stimulus in Microprocessor Emulation Model Feedback Using a Shared Memory 失效
标题翻译：在微处理器仿真模型反馈中使用共享存储器并入设计行为和外部激励的系统和方法
公开(公告)号：US20080167854A1
公开(公告)日：2008-07-10
申请号：US11621335
申请日：2007-01-09
申请人： Sanjay Gupta , Joseph Anthony Perrie , Steven Leonard Roberts , Todd Swanson
发明人： Sanjay Gupta , Joseph Anthony Perrie , Steven Leonard Roberts , Todd Swanson
IPC分类号： G06F9/455
CPC分类号： G06F17/5022
摘要： A system and method for incorporating design behavior and external stimulus in microdevice model feedback using a shared memory is presented. The invention describe herein uses the attached memory model to provide additional heuristics to an application executing on an emulation system's device model, which results in a more detail and real-life device emulation. The attached memory model provides a storage area for a runtime software environment to store emulation data, which is subsequently provided to the device model during emulation. The emulation data may include 1) randomization stimuli to the device model, 2) additional runtime data for checking heuristics, and 3) emulation data points that are otherwise not accessible to the device model.
摘要翻译：提出了一种使用共享存储器将设计行为和外部刺激并入微设计模型反馈的系统和方法。本文描述的本发明使用附加的存储器模型来为在仿真系统的设备模型上执行的应用提供附加启发式，这导致更细节和真实的设备仿真。附加的存储器模型为运行时软件环境提供存储区域以存储仿真数据，随后在仿真期间将其提供给设备模型。仿真数据可以包括1）对设备模型的随机化刺激，2）用于检查启发式的附加运行时间数据，以及3）设备模型否则不可访问的仿真数据点。

9. 发明授权

US07627843B2 Dynamically interleaving randomly generated test-cases for functional verification 失效
标题翻译：随机生成测试用例的动态交织功能验证
公开(公告)号：US07627843B2
公开(公告)日：2009-12-01
申请号：US11087466
申请日：2005-03-23
申请人： Igor Dozorets , Roy Emek , Sanjay Gupta , Itai Jaeger , Lawrence Allyn McConville , Tzach Schechner , Todd Swanson
发明人： Igor Dozorets , Roy Emek , Sanjay Gupta , Itai Jaeger , Lawrence Allyn McConville , Tzach Schechner , Todd Swanson
IPC分类号： G06F9/00
CPC分类号： G06F17/5022 , G01R31/318371
摘要： The input for a test generator is a plurality of test templates, each of which typically aims at covering a specific verification task. Test templates direct the production of distinct transactions, which are the atomic functional building blocks of the design-under-verification. Test templates directed to different hardware functions of the scenario are dynamically interleaved. In this way several transactions are combined together in complex statements in order to achieve a complex test scenario. The transactions are submitted to the test generator, which generates test cases, in which the different hardware functions of the scenario are exercised in combinations. Variation among the test cases is achieved through a large number of random decisions made during the generation process.
摘要翻译：测试发生器的输入是多个测试模板，每个测试模板通常旨在覆盖特定的验证任务。测试模板可以直接生成不同的事务，这是不合格设计的原子功能构建块。定向到场景的不同硬件功能的测试模板是动态交错的。以这种方式，在复杂语句中将多个事务合并在一起，以实现复杂的测试场景。这些事务被提交给测试发生器，该测试发生器生成测试用例，其中组合运行该场景的不同硬件功能。测试用例之间的变化是通过在生成过程中做出的大量随机决策来实现的。

10. 发明申请

US20060218513A1 Dynamically interleaving randomly generated test-cases for functional verification 失效
公开(公告)号：US20060218513A1
公开(公告)日：2006-09-28
申请号：US11087466
申请日：2005-03-23
申请人： Igor Dozorets , Roy Emek , Sanjay Gupta , Itai Jaeger , Lawrence McConville , Tzach Schechner , Todd Swanson
发明人： Igor Dozorets , Roy Emek , Sanjay Gupta , Itai Jaeger , Lawrence McConville , Tzach Schechner , Todd Swanson
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022 , G01R31/318371
摘要： The input for a test generator is a plurality of test templates, each of which typically aims at covering a specific verification task. Test templates direct the production of distinct transactions, which are the atomic functional building blocks of the design-under-verification. Test templates directed to different hardware functions of the scenario are dynamically interleaved. In this way several transactions are combined together in complex statements in order to achieve a complex test scenario. The transactions are submitted to the test generator, which generates test cases, in which the different hardware functions of the scenario are exercised in combinations. Variation among the test cases is achieved through a large number of random decisions made during the generation process.

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