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1. 发明授权

US07801079B2 Method and apparatus for battery-aware dynamic bandwidth allocation for groups of wireless sensor nodes in a wireless sensor network 有权
标题翻译：无线传感器网络中无线传感器节点组的电池感知动态带宽分配的方法和装置
公开(公告)号：US07801079B2
公开(公告)日：2010-09-21
申请号：US11681634
申请日：2007-03-02
申请人： Ali Saidi , Silviu Chiricescu , Philip E. May , Kent D. Moat
发明人： Ali Saidi , Silviu Chiricescu , Philip E. May , Kent D. Moat
IPC分类号： H04W4/00 , H04B7/212
CPC分类号： G01D21/00 , H04W4/06 , H04W52/0261 , H04W72/085 , H04W84/18
摘要： A method and apparatus that allocates bandwidth among wireless sensor nodes in wireless sensor groups in a wireless sensor network (WSN) is disclosed. The method may include forming a plurality of wireless sensor node groups from a plurality of wireless sensor nodes based on battery levels of the wireless senor nodes, allocating transmission time slots for the wireless sensor nodes in each of the wireless sensor node groups based on at least one channel quality metric, determining average battery levels for each of the wireless sensor node groups and average battery level of all of the wireless sensor nodes, determining differences between the average battery levels of each of the wireless sensor node groups and the average battery level of all of the wireless sensor nodes, wherein if any difference in the average battery levels is above a predetermined threshold, regrouping the plurality of wireless sensor nodes according to the battery levels of the plurality wireless sensor nodes to minimize any variance in average battery level across all of the wireless sensor node groups.
摘要翻译：公开了一种在无线传感器网络（WSN）中的无线传感器组中的无线传感器节点之间分配带宽的方法和装置。该方法可以包括基于无线传感器节点的电池电平从多个无线传感器节点形成多个无线传感器节点组，至少基于至少基于无线传感器节点组中的无线传感器节点组中的无线传感器节点分配传输时隙单通道质量度量，确定每个无线传感器节点组的平均电池电量和所有无线传感器节点的平均电池电量，确定每个无线传感器节点组的平均电池电量与平均电池电量之间的差异所有无线传感器节点，其中如果平均电池电平中的任何差异高于预定阈值，则根据多个无线传感器节点的电池电平重新分组多个无线传感器节点，以最小化所有的平均电池电平的任何差异的无线传感器节点组。

2. 发明申请

US20080211666A1 METHOD AND APPARATUS FOR BATTERY-AWARE DYNAMIC BANDWIDTH ALLOCATION FOR GROUPS OF WIRELESS SENSOR NODES IN A WIRELESS SENSOR NETWORK 有权
标题翻译：无线传感器网络无线传感器组的电池动态带宽分配方法与装置
公开(公告)号：US20080211666A1
公开(公告)日：2008-09-04
申请号：US11681634
申请日：2007-03-02
申请人： Ali Saidi , Silviu Chiricescu , Philip E. May , Kent D. Moat
发明人： Ali Saidi , Silviu Chiricescu , Philip E. May , Kent D. Moat
IPC分类号： H04Q7/00 , G08B19/00 , H04B7/00
CPC分类号： G01D21/00 , H04W4/06 , H04W52/0261 , H04W72/085 , H04W84/18
摘要： A method and apparatus that allocates bandwidth among wireless sensor nodes in wireless sensor groups in a wireless sensor network (WSN) is disclosed. The method may include forming a plurality of wireless sensor node groups from a plurality of wireless sensor nodes based on battery levels of the wireless senor nodes, allocating transmission time slots for the wireless sensor nodes in each of the wireless sensor node groups based on at least one channel quality metric, determining average battery levels for each of the wireless sensor node groups and average battery level of all of the wireless sensor nodes, determining differences between the average battery levels of each of the wireless sensor node groups and the average battery level of all of the wireless sensor nodes, wherein if any difference in the average battery levels is above a predetermined threshold, regrouping the plurality of wireless sensor nodes according to the battery levels of the plurality wireless sensor nodes to minimize any variance in average battery level across all of the wireless sensor node groups.
摘要翻译：公开了一种在无线传感器网络（WSN）中的无线传感器组中的无线传感器节点之间分配带宽的方法和装置。该方法可以包括基于无线传感器节点的电池电平从多个无线传感器节点形成多个无线传感器节点组，至少基于至少基于无线传感器节点组中的无线传感器节点组中的无线传感器节点分配传输时隙单通道质量度量，确定每个无线传感器节点组的平均电池电量和所有无线传感器节点的平均电池电量，确定每个无线传感器节点组的平均电池电量与平均电池电量之间的差异所有无线传感器节点，其中如果平均电池电平中的任何差异高于预定阈值，则根据多个无线传感器节点的电池电平重新分组多个无线传感器节点，以最小化所有的平均电池电平的任何差异的无线传感器节点组。

3. 发明授权

US07290122B2 Dataflow graph compression for power reduction in a vector processor 有权
标题翻译：用于矢量处理器中功率降低的数据流图压缩
公开(公告)号：US07290122B2
公开(公告)日：2007-10-30
申请号：US10652134
申请日：2003-08-29
申请人： Philip E. May , Brian G. Lucas , Kent D. Moat
发明人： Philip E. May , Brian G. Lucas , Kent D. Moat
IPC分类号： G06F9/308 , G06F15/18
CPC分类号： G06F9/3853 , G06F1/3203 , G06F1/3275 , G06F1/3287 , G06F9/3017 , G06F9/3885 , Y02D10/14 , Y02D10/171
摘要： A method and apparatus for power reduction in a processor controlled by multiple-instruction control words. A multiple-instruction control word comprises a number of ordered fields, with each ordered field containing an instruction for an element of the processor. The sequence of instructions for a loop is compressed by identifying a set of aligned fields that contain NOP instructions in all of the control words of the sequence. The sequence of control words is then modified by removing the fields of the identified aligned set containing NOP instructions and adding an identifier that identifies the set of fields removed. The sequence of control words is processed by fetching the identifier at the start the loop, then, for each control word in the sequence, fetching a control word and reconstructing the corresponding uncompressed control word by inserting NOP instructions into the compressed control word as indicated by the identifier. The identifier may be a bit mask and may used to disable memory units and processing elements for the duration of the loop to reduce power consumption by the processor.
摘要翻译：一种用于由多指令控制字控制的处理器中的功率降低的方法和装置。多指令控制字包括多个有序字段，每个有序字段包含用于处理器的元素的指令。通过在序列的所有控制字中识别包含NOP指令的一组对齐的字段来压缩循环的指令序列。然后通过去除包含NOP指令的所识别的对齐集合的字段来添加控制字的序列，并添加标识删除的字段的标识符。控制字的序列通过在循环开始时取出标识符来处理，然后，对于序列中的每个控制字，通过将NOP指令插入到压缩控制字中来获取控制字并重建相应的未压缩控制字，如标识符。标识符可以是位掩码，并且可以用于在循环的持续时间内禁用存储器单元和处理元件以减少处理器的功耗。

4. 发明授权

US07246203B2 Queuing cache for vectors with elements in predictable order 有权
标题翻译：用可预测顺序的元素排队缓存
公开(公告)号：US07246203B2
公开(公告)日：2007-07-17
申请号：US10993972
申请日：2004-11-19
申请人： Kent D. Moat , Raymond B. Essick, IV , Philip E. May , James M. Norris
发明人： Kent D. Moat , Raymond B. Essick, IV , Philip E. May , James M. Norris
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/126
摘要： A cache for storing data elements is disclosed. The cache includes a cache memory having one or more lines and one or more cache line counters, each associated with a line of the cache memory. In operation, a cache line counter of the one or more of cache line counters is incremented when a request is received to prefetch a data element into the cache memory and is decremented when the data element is consumed. Optionally, one or more reference queues may be used to store the locations of data elements in the cache memory. In one embodiment, data cannot be evicted from cache lines unless the associated cache line counters indicate that the prefetched data has been consumed.
摘要翻译：公开了一种用于存储数据元素的缓存。高速缓存包括具有一行或多行和一个或多个高速缓存行计数器的高速缓冲存储器，每个缓存行计数器与高速缓冲存储器的一行相关联。在操作中，当接收到请求以将数据元素预取入高速缓冲存储器时，高速缓存行计数器中的一个或多个的高速缓存行计数器递增，并且当数据元素被消耗时递减。可选地，可以使用一个或多个参考队列来存储高速缓冲存储器中的数据元素的位置。在一个实施例中，除非相关联的高速缓存行计数器指示预取的数据已被消耗，否则数据不能从高速缓存行逐出。

5. 发明授权

US07415601B2 Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters 失效
标题翻译：用于使用数据有效性标签和接收器计数器消除矢量处理器中的序言和epilog指令的方法和装置
公开(公告)号：US07415601B2
公开(公告)日：2008-08-19
申请号：US10652135
申请日：2003-08-29
申请人： Philip E. May , Raymond B. Essick, IV , Brian G. Lucas , Kent D. Moat , James M. Norris
发明人： Philip E. May , Raymond B. Essick, IV , Brian G. Lucas , Kent D. Moat , James M. Norris
IPC分类号： G06F9/30
CPC分类号： G06F9/3889 , G06F9/30036 , G06F9/30105 , G06F9/325 , G06F9/3824 , G06F9/3859
摘要： A method and apparatus for the elimination of prolog and epilog instructions in a vector processor. To eliminate the prolog, a functional unit of the vector processor has at least one input for receiving an input data value tagged with a data validity tag and an output for outputting an intermediate result tagged with a data validity tag. The data validity tags indicate the validity of the data. Before a loop is executed, the data validity tags are set to indicate that the associated data values are invalid. During execution of the loop body a functional unit checks the validity of input data. If all of the input data values are valid the functional operation is performed, the corresponding data validity tag set to indicate that the result is valid. If any of the input data values is invalid, the data validity tag of the result is set to indicate that the result is invalid. To eliminate the epilog, an iteration counter is associated with each sink unit of the vector processor. When a specified number of data values have been produced by a particular sink, no more data values are produced by that sink. The instructions for the pipelined loop body may be repeated, without alteration, to eliminate prolog and epilog instructions.
摘要翻译：用于消除向量处理器中的序言和外延指令的方法和装置。为了消除序言，矢量处理器的功能单元具有至少一个用于接收标记有数据有效性标签的输入数据值的输入和用于输出用数据有效性标签标记的中间结果的输出。数据有效性标签表示数据的有效性。在执行循环之前，数据有效性标签被设置为指示相关联的数据值无效。在执行循环体期间，功能单元检查输入数据的有效性。如果所有输入数据值都有效，则执行功能操作，设置相应的数据有效性标签以指示结果有效。如果任何输入数据值无效，则将结果的数据有效性标签设置为指示结果无效。为了消除epilog，迭代计数器与向量处理器的每个宿单元相关联。当特定接收器产生指定数量的数据值时，该接收器不会产生更多的数据值。流水线回路体的指令可以重复进行，而无需改变，以消除序言和epilog指令。

6. 发明授权

US07100019B2 Method and apparatus for addressing a vector of elements in a partitioned memory using stride, skip and span values 失效
标题翻译：使用步幅，跳跃和跨度值来寻址分割存储器中的元素向量的方法和装置
公开(公告)号：US07100019B2
公开(公告)日：2006-08-29
申请号：US10657793
申请日：2003-09-08
申请人： James M. Norris , Philip E. May , Kent D. Moat , Raymond B. Essick, IV , Brian G. Lucas
发明人： James M. Norris , Philip E. May , Kent D. Moat , Raymond B. Essick, IV , Brian G. Lucas
IPC分类号： G06F15/00 , G06F12/00
CPC分类号： G06F9/3552 , G06F9/30036 , G06F9/345 , G06F9/3455 , G06F9/3824 , G06F9/383 , G06F9/3877 , G06F9/3879 , G06F15/7867 , G06F15/8061
摘要： A system and method for calculating memory addresses in a partitioned memory in a processing system having a processing unit, input and output units, a program sequencer and an external interface. An address calculator includes a set of storage elements, such as registers, and an arithmetic unit for calculating a memory address of a vector element dependent upon values stored in the storage elements and the address of a previous vector element. The storage elements hold STRIDE, SKIP and SPAN values and optionally a TYPE value, relating to the spacing between elements in the same partition, the spacing between elements in the consecutive partitions, the number of elements in a partition and the size of a vector element, respectively.
摘要翻译：一种用于在具有处理单元，输入和输出单元，程序定序器和外部接口的处理系统中计算分区存储器中的存储器地址的系统和方法。地址计算器包括诸如寄存器的一组存储元件，以及用于根据存储在存储元件中的值和先前矢量元素的地址来计算向量元素的存储器地址的算术单元。存储元件保持STRIDE，SKIP和SPAN值以及可选的TYPE值，与相同分区中的元素之间的间隔相关，连续分区中的元素间距，分区中的元素数量和向量元素的大小，分别。

7. 发明授权

US07945768B2 Method and apparatus for nested instruction looping using implicit predicates 有权
标题翻译：使用隐式谓词的嵌套指令循环的方法和装置
公开(公告)号：US07945768B2
公开(公告)日：2011-05-17
申请号：US12133885
申请日：2008-06-05
申请人： Raymond B. Essick, IV , Kent D. Moat , Michael A. Schuette
发明人： Raymond B. Essick, IV , Kent D. Moat , Michael A. Schuette
IPC分类号： G06F9/00
CPC分类号： G06F9/325 , G06F9/30072
摘要： A method and apparatus for executing a nested program loop on a vector processor, the loop comprising outer-pre, inner and outer-post portions. An input stream unit of the vector processor provides a data value to a data path and sets an associated data validity tag to ‘valid’ once per outer loop iteration, as indicated by an inner counter of the input stream unit. The tag is set to ‘invalid’ in other iterations. Functional units of the vector processor operate on data values in the data path, each functional unit producing a valid result if the data validity tags associated with inputs data values are set to ‘valid’. An output stream unit of the vector processor sinks a data value from the data path once per outer loop iteration if an associated data validity tag indicates that the data value is valid.
摘要翻译：一种用于在矢量处理器上执行嵌套程序循环的方法和装置，所述循环包括外部前部，内部和后部部分。矢量处理器的输入流单元向数据路径提供数据值，并且如外部循环迭代一样，将相关联的数据有效性标签设置为“有效”，如输入流单元的内部计数器所示。标签在其他迭代中设置为“无效”。如果与输入数据值相关联的数据有效性标签设置为“有效”，则向量处理器的功能单元对数据路径中的数据值进行操作，每个功能单元产生有效结果。如果相关联的数据有效性标签指示数据值有效，则向量处理器的输出流单元从每个外部循环迭代从数据路径中收集数据值一次。

8. 发明申请

US20090307472A1 Method and Apparatus for Nested Instruction Looping Using Implicit Predicates 有权
标题翻译：使用隐式谓词的嵌套指令循环的方法和装置
公开(公告)号：US20090307472A1
公开(公告)日：2009-12-10
申请号：US12133885
申请日：2008-06-05
申请人： Raymond B. Essick IV , Kent D. Moat , Michael A. Schuette
发明人： Raymond B. Essick IV , Kent D. Moat , Michael A. Schuette
IPC分类号： G06F9/30
CPC分类号： G06F9/325 , G06F9/30072
摘要： A method and apparatus for executing a nested program loop on a vector processor, the loop comprising outer-pre, inner and outer-post portions. An input stream unit of the vector processor provides a data value to a data path and sets an associated data validity tag to ‘valid’ once per outer loop iteration, as indicated by an inner counter of the input stream unit. The tag is set to ‘invalid’ in other iterations. Functional units of the vector processor operate on data values in the data path, each functional unit producing a valid result if the data validity tags associated with inputs data values are set to ‘valid’. An output stream unit of the vector processor sinks a data value from the data path once per outer loop iteration if an associated data validity tag indicates that the data value is valid.
摘要翻译：一种用于在矢量处理器上执行嵌套程序循环的方法和装置，所述循环包括外部前部，内部和后部部分。向量处理器的输入流单元向数据路径提供数据值，并且如外部循环迭代一样，将相关联的数据有效性标签设置为“有效”，如输入流单元的内部计数器所示。标签在其他迭代中设置为“无效”。如果与输入数据值相关联的数据有效性标签设置为“有效”，则向量处理器的功能单元对数据路径中的数据值进行操作，每个功能单元产生有效结果。如果相关联的数据有效性标签指示数据值有效，则向量处理器的输出流单元从每个外部循环迭代从数据路径中收集数据值一次。

9. 发明申请

US20080250499A1 Method and Apparatus for Reducing Buffer Overflow Exploits by Computer Viruses 审中-公开
标题翻译：用于减少计算机病毒的缓冲区溢出漏洞的方法和装置
公开(公告)号：US20080250499A1
公开(公告)日：2008-10-09
申请号：US11694672
申请日：2007-03-30
申请人： Kent D. Moat , Ronald F. Buskey , Brian G. Lucas
发明人： Kent D. Moat , Ronald F. Buskey , Brian G. Lucas
IPC分类号： G06F21/00
CPC分类号： G06F21/566
摘要： Buffer overflow exploits in a computer are reduced by encoding linkage information associated with a subroutine, following a call to the subroutine from an application executing on the computer. The encoded linkage information is stored at a first address in a run-time stack in a memory of the computer. Upon exit from the subroutine, the value stored at the first address in the run-time stack is retrieved and decoded to obtain decoded linkage information. Execution of the application continues in accordance with the decoded linkage information. Subroutine data written to the stack is not encoded.
摘要翻译：在从计算机上执行的应用程序调用子程序之后，通过编码与子程序相关联的链接信息来减少计算机中的缓冲区溢出漏洞利用。编码的链接信息被存储在计算机的存储器中的运行时栈中的第一地址处。在从子程序退出时，检索并解码存储在运行时堆栈中的第一地址处的值，以获得解码的链接信息。应用程序的执行根据解码的链接信息继续。写入堆栈的子程序数据不进行编码。

10. 发明授权

US07502909B2 Memory address generation with non-harmonic indexing 有权
标题翻译：具有非谐波索引的存储器地址生成
公开(公告)号：US07502909B2
公开(公告)日：2009-03-10
申请号：US11247425
申请日：2005-10-11
申请人： Kent D. Moat , Raymond B. Essick , Michael A. Schuette
发明人： Kent D. Moat , Raymond B. Essick , Michael A. Schuette
IPC分类号： G06F12/00
CPC分类号： G06F9/345 , G06F9/3455
摘要： A method for generating a sequence of memory addresses for a multi-dimensional data structure and an address generation unit are disclosed. The address generation unit includes an ADDRESS register, a STRIDE register, and a plurality skip generators, each having SKIP, SPAN and COUNT registers. An address value is initialized to a first address and each COUNT register is initialized. For each address of the sequence an address value is output and a stride value is added to the address value. For each dimension of the data structure the COUNT register associated with the dimension is updated as each address is generated. For all dimensions, when the COUNT register value becomes zero, the skip value associated with the dimension is added to the address value and its COUNT register is reset to a specified value.
摘要翻译：公开了一种用于生成多维数据结构和地址生成单元的存储器地址序列的方法。地址生成单元包括地址寄存器，STRIDE寄存器和多个跳过发生器，每个具有SKIP，SPAN和COUNT寄存器。地址值被初始化为第一个地址，并且每个COUNT寄存器被初始化。对于序列的每个地址，输出地址值，并将stride值添加到地址值。对于数据结构的每个维度，与维度相关联的COUNT寄存器随着生成每个地址而被更新。对于所有维度，当COUNT寄存器值为零时，与维度相关联的跳过值将添加到地址值，并将其COUNT寄存器重置为指定值。

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